Message196713
| Author | neologix |
|---|---|
| Recipients | neologix, pitrou, rhettinger, tim.peters, vstinner |
| Date | 2013-09-01.07:30:38 |
| SpamBayes Score | -1.0 |
| Marked as misclassified | Yes |
| Message-id | <1378020638.92.0.121235505145.issue18835@psf.upfronthosting.co.za> |
| In-reply-to |
| Content | |
|---|---|
> Please don't FUD this one to death. Aligned memory access is > sometimes important and we currently have no straight-forward > way to achieve it. I guess that a simple way to cut the discussion short would be to have a first implementation, and run some benchmarks to measure the benefits. I can certainly see the benefit of cacheline-aligned data structures in multithreaded code (to avoid false sharing/cacheline bouncing): I'm really curious to see how much this would benefit in a single-threaded workload. |
|
| History | |||
|---|---|---|---|
| Date | User | Action | Args |
| 2013-09-01 07:30:38 | neologix | set | recipients: + neologix, tim.peters, rhettinger, pitrou, vstinner |
| 2013-09-01 07:30:38 | neologix | set | messageid: <1378020638.92.0.121235505145.issue18835@psf.upfronthosting.co.za> |
| 2013-09-01 07:30:38 | neologix | link | issue18835 messages |
| 2013-09-01 07:30:38 | neologix | create | |