Add riscv64 (linux_riscv64) wheel to PyPI releases
Summary
pip install pillow on riscv64 Linux currently requires building from source (~5 min on a 1.6 GHz RISC-V SoC). Adding linux_riscv64 to the wheel build matrix would give riscv64 users a prebuilt wheel.
Evidence
| Tested wheel | pillow-12.1.1-cp313-cp313-linux_riscv64.whl |
| Hardware | BananaPi F3 (SpacemiT K1, rv64imafdcv, 8 cores @ 1.6 GHz, 16 GB RAM) |
| Python | 3.13 (CPython) |
| Build system | cibuildwheel |
| Build time | ~5 min (native, on hardware) |
The wheel imports and passes basic smoke tests on riscv64 Linux.
Suggested CI change
Workflow: .github/workflows/wheels.yml
Add riscv64 entries to the build-native-wheels matrix:
# In matrix.include, add: - name: "manylinux_2_28 riscv64" platform: linux os: ubuntu-latest cibw_arch: riscv64 build: "*manylinux*"
Add QEMU step (after checkout, before cibuildwheel):
- name: Set up QEMU if: matrix.cibw_arch == 'riscv64' uses: docker/setup-qemu-action@v3 with: platforms: riscv64
Ecosystem context
manylinux_2_28_riscv64images are available onquay.io/pypa/(landed in pypa/manylinux, 2025)- cibuildwheel 3.x supports riscv64 via QEMU emulation
- auditwheel supports riscv64 platform tags
- maturin-action supports
riscv64gc-unknown-linux-gnucross-compilation - Packages already shipping riscv64 wheels on PyPI: aiohttp, yarl, regex, markupsafe, charset-normalizer, rpds-py, multidict, propcache, watchfiles, rignore, setproctitle
- RISC-V hardware is shipping: SiFive HiFive, SpacemiT K1/K3, Sophgo SG2044 (64-core)
Our temporary index
While upstream support is pending, we maintain a PEP 503 index with 50+ riscv64 wheels for the Python ML/AI stack, built natively on RISC-V hardware.
Tracking repo: https://github.com/gounthar/riscv64-python-wheels