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UC Berkeley Architecture Research

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  1. An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 2.2k 848

  2. chisel tutorial exercises and answers

    Scala 751 200

  3. Berkeley's Spatial Array Generator

    Scala 1.3k 256

  4. Hammer: Highly Agile Masks Made Effortlessly from RTL

    Python 315 76

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Showing 10 of 213 repositories

  • autocomp Public

    Autocomp: Optimize any AI kernel, anywhere.

    ucb-bar/autocomp’s past year of commit activity

  • ucb-bar/XPU-RT’s past year of commit activity

    Python

    3 1 0 0

    Updated Apr 18, 2026

  • iree Public Forked from iree-org/iree

    A retargetable MLIR-based machine learning compiler and runtime toolkit.

    ucb-bar/iree’s past year of commit activity

    C++ 0 Apache-2.0

    911 0 7

    Updated Apr 17, 2026

  • merlin Public

    MLIR-in as a compiler stack for ucb-bar

    ucb-bar/merlin’s past year of commit activity

    MLIR

    12

    Apache-2.0

    2 3 3

    Updated Apr 17, 2026

  • ucb-bar/Understanding-PI0’s past year of commit activity

    HTML

    4

    0

    0 0

    Updated Apr 17, 2026

  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    ucb-bar/chipyard’s past year of commit activity

  • MxGen Public

    Configurable low-precision floating-point and microscaling hardware in Chisel

    ucb-bar/MxGen’s past year of commit activity

    Scala

    2

    0

    0 0

    Updated Apr 17, 2026

  • ucie Public

    An open-source UCIe implementation

    ucb-bar/ucie’s past year of commit activity

    Scala

    93

    BSD-3-Clause

    20 0 1

    Updated Apr 17, 2026

  • ucb-bar/saturn-vectors’s past year of commit activity

    Assembly

    143

    BSD-3-Clause

    30 8 1

    Updated Apr 10, 2026

  • ucb-bar/testchipip’s past year of commit activity