64K by 1 bit, in a particular pin configuration ('pinout').
64K by 1 bit = 65,536 bits

Note that some makers did not use "4164" in their part number.  That is because makers did not need to adhere to a common naming standard.  Some makers may have even purposely not used 4164 to avoid possible litigation action.

DIP packages (of plastic and ceramic) listed only - LCC and SIP packages are omitted.

Japanese makers tend not to print prefixes on ICs and transistors.  In photos below, it is seen that at least Mitsubishi, NEC, and Oki are in that category for the 4164.

The CMOS version of the 4164 class appears to be the 5164 class.

Pin 1 use

On the majority of 4164 type chips, pin 1 is unused - data sheets indicate that the pin is "N.C." (Not Connected).  See here.
Pin 1 on the remaining chips is used to allow selection of additional refresh modes (MCM6664A data sheet below indicates 'automatic' and 'self-refresh').

Refresh Cycles

Two types.
    • 256cycle/4ms: Refreshes to rows 0 through 255, within a 4 millisecond limit, will result in all 65,536 cells (bits) being refreshed.
    • 128cycle/2ms: Refreshes to rows 0 through 127, within a 2 millisecond limit, will result in all 65,536 cells (bits) being refreshed.

Some computer systems may specify chips of the 128 cycles type only.  Presumably, that is because the system's refresh circuitry only counts as high as row 127.  Placing 256cycle/4ms chips in such a system would fail because rows 128 to 255 in those chips would not be refreshed.  More information is at here.

The '256cycle/4ms' chips will have a cell matrix of 256 rows by 256 columns.  The '128cycle/2ms' chips will have a cell matrix of 128 rows by 512 columns.  For more information, see the 'Rectangular cell matrices' section of here.