Languages

2.5D

Multiple chips arranged in a planar or stacked configuration with an interposer for communication.

Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.

Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.

In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.

In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.

One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.

The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.

Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.

Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.

Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a “macaroni channel,” according to Objective Analysis.

Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.

Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.

3D Transistors

Transistors where source and drain are added as fins of the gate.

3D-ICs

2.5D and 3D forms of integration

5G

Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.

Acronyms

Commonly and not-so-commonly used acronyms.
The following is a list of acronyms and what they stand for:

ACK - Acknowledge
ADC - Analog to Digital Converter
AI - Artificial Intelligence
ALD - Atomic Layer Deposition
ALE - Atomic Layer Etch
AMOLED - Active-Matrix OLED
AMP - Asymmetric Multi Processing
AOI - Automated Optical Inspection
AP - Access Point
ASIC - Application Specific Integrated Circuit
ATE - Automatic Test Equipment
BEOL - Back-End-Of-Line
BGA - Ball Grid Array
BSA - Basic Service Area
BTI - Bias-Temperature Instability
CA - Collision Avoidance
CBRAM - Conductive Bridging RAM
CCI - Cache Coherent Interconnect
CD Collision Detection
CF - Contention-Free
CFP - Contention-Free Period
CP - Contention Period
CPU - Central Processing Unit
CRC - Cyclic Redundancy Check
CSMA - Carrier Sense, Multiple Access
CFD - Computational Fluid Dynamic
CMOS - Complementary Metal Oxide Semiconductor
CNN - Convolutional Neural Network
CPP - Contacted Poly Pitch
CSP - Chip Scale Packaging
CTS - Clear To Send
DAC - Digital to Analog Convertor
DARPA - Defense Advanced Research Projects Agency
DCF - Distributed Coordination Function
DDR - Double Data Rate
DFA - Differential Fault Analysis
DFT - Design for Test
DFM - Design for Manufacturing
DIFS - Distributed Inter-frame Space
DPA - Differential Power Analysis
DL - Deep Learning
DRAM - Dynamic Random Access Memory
DRC - Design Rule Checker
DSA - Directed Self Assembly
DSP - Digital Signal Processor
DUT - Design Under Test
DUV - Design Under Verification
DVFS - Dynamic Voltage and Frequency Scaling
ECO - Engineering Change Order
EDA - Electronic Design Automation
EM - Electromagnetic
EM - Electromigration
ESL - Electronic System Level
EUV - Extreme Ultraviolet
FD-SOI - Fully Depleted Silicon on Insulator
FEOL - Front-End-Of-Line
FET - Field Effect Transistor
FIFO - First In First Out
FPGA - Field Programmable Gate Array
GAA - Gate-All-Around
GaAs - Gallium Arsenide
GaN - Gallium Nitride
GPU - Graphics Processing Unit
HBM - High Bandwidth Memory
HBT - Heterojunction Bipolar Transistor
HDL - Hardware Description Language
HMC - Hybrid Memory Cube
IC - Integrated Circuit
IEEE - Institute of Electrical and Electronics Engineers
IIC - Industrial Internet Consortium
IIoT - Industrial Internet of Things
IoT - Internet of Things
IP - Intellectual Property
IR - Infra-red
ISM - Industrial, Scientific, Medical
ISS - Instruction Set Simulator
ILT - Inverse Lithography Technology
JTAG - Joint Test Action Group
LAN - Local Area Network
LCD - Liquid Crystal Display
LTE - Long-Term Evolution
MAC -Media Access Control
MCU - Microcontroller
MEMS - Micro Electrical Mechanical Systems
MES - Manufacturing Execution Systems
ML-Machine Learning
MOL - Middle-Of-Line
MRAM - Magnetic Random Access Memory
NA - Numerical Aperture
NGL - Next-Generation Lithography
NIC - Network Interface Card
NSF - National Science Foundation
NVM - Non-Volatile Memory
OCAP - Out of Control Action Plan
OLED - Organic Light-Emitting Diode
OPC - Optical Proximity Correction
OS - Operating System
OSAT - Outsourced Semiconductor Assembly and Test
OTP - One Time Programmable
PCB - Printed Circuit Board
PCF - Point Coordination Function
PCM - Phase-Change Memory
PDK - Process Design Kit
PDN - Power Delivery Network
PHY - Physical Layer
PI - Power Integrity
PIFS - Point Inter-frame Space
PnR - Place and Route
PoP - Package-on-Package
PPA - Power, Performance, Area
PPAC - Power, Performance, Area, Cost
PRNG - Pure Random Number Generator
PVT - Process, Voltage, Temperature
RAM - Random Access Memory
RC4 - Rivest Cipher 4
RDL - Register Definition Language
RDL - Redistribution Layer
RF - Radio Frequency
ROM - Read Only Memory
RoT - Root Of Trust
RTL - Register Transfer Level
RTOS - Real Time Operating System
RTS - Request To Send
SCM - Storage Class Memory
SerDes - Serializer / Deserializer
SIFS - Short Inter-frame Space
SI - Signal Integrity
SiC - Silicon Carbide
SiGe - Silicon Germanium
SK - Shared Key
SMP - Symmetric Multi Processing
SoC - System on Chip
SOI - Silicon on Insulator
SPA - Simple Power Analysis
SRAF - Sub-Resolution Assist Features
SRAM - Static Random Access Memory
SSD - Solid-state Storage Drives
SSID - Service Set Identifier
STA - Static Timing Analysis
STI - Shallow Trench Isolation
TLM - Transaction Level Model
TSV - Through Silicon Via
UPF - Unified Power Format
USB - Universal Serial Bus
UVM - Universal Verification Methodology
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
VSLI - Very Large Scale Integration
VIP - Verification Intellectual Property
VoWi-Fi - Voice over Wi-Fi
Vt - theshold Voltage
Wan - Wide Area Network
WEP - Wired Equivalency Protocol
Wi-Fi - Wireless High Fidelity
WiGIG - Gigabit Wi-Fi
WLAN - Wireless Local Area Network
WLP - Wafer Level Packaging
WPA - Wi-Fi Protected Access

Advanced Packaging

Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.

While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.

These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.

Agile

An approach to software development focusing on continual delivery and flexibility to changing requirements

Air Gap

A way of improving the insulation between various components in a semiconductor by creating empty space.

Amdahl’s Law

The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.

Analog

Semiconductors that measure real-world conditions

Analog circuits

Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.

Assertion

Code that looks for violations of a property

Atomic Layer Etch (ALE)

ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.

Automotive

Issues dealing with the development of automotive electronics.

AVM

Verification methodology created by Mentor

Batteries

Devices that chemically store energy.

C, C++

C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.

Characterization/Metrology Lab

A lab that wrks with R&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.

Checker

Testbench component that verifies results

Chip Design

Design is the process of producing an implementation from a conceptual form

Chiplets

A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.

There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.

With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.

A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.

Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandou’s chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandou’s interconnect technology.

DARPA’s approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.

The CHIPS program started in 2017. The program has various types of contractors/sub-contractors—manufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).

CMOS

Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.

CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.

Code Coverage

Metrics related to about of code executed in functional verification

Contact

The structure that connects a transistor with the first layer of copper interconnects.

Coverage

Completion metrics for functional verification

Crypto processors

Crypto processors are specialized processors that execute cryptographic algorithms within hardware.

Dark Silicon

A method of conserving power in ICs by powering down segments of a chip when they are not in use.

Data Analytics

Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.

Data Analytics & Test

How semiconductors are sorted and tested before and after implementation of the chip in a system.

Data Movement

The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.

Debug

The removal of bugs from a design

Deep Learning (DL)

Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.

Dennard’s Law

An observation that as features shrink, so does power consumption.

Design for Manufacturing (DFM)

Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.

Design for Test (DFT)

Techniques that reduce the difficulty and cost associated with testing an integrated circuit.

Design Rule Checking (DRC)

A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer

DRAM: Dynamic Random Access Memory

Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.

Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.

In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.

DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.

Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.

The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.

Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these

The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.

e

Hardware Verification Language

Electronic Design Automation (EDA)

Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.

Embedded FPGA (eFPGA)

An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.

Emulation

Special purpose hardware used for logic verification

Epitaxy

A method for growing or depositing mono crystalline films on a substrate.

eRM

Reuse methodology based on the e language

Ethernet

Ethernet is a reliable, open standard for connecting devices by wire.

Failure Analysis

Finding out what went wrong in semiconductor design and manufacturing.

Fan-Outs

A way of including more features that normally would be on a printed circuit board inside a package.

Fault Simulation

Evaluation of a design under the presence of manufacturing defects

FinFET

A three-dimensional transistor.

Flash Memory

Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.

The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.

Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.

With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.

Flip-Chip

A type of interconnect using solder balls or microbumps.

Formal Verification

Formal verification involves a mathematical proof to show that a design adheres to a property

Functional Verification

Functional verification is used to determine if a design, or unit of a design, conforms to its specification.

Germany

Germany is known for its automotive industry and industrial machinery.

Graphene

Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.

The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.

Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2⋅V−1⋅s−1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.

While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.

Guard Banding

Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.

Hard IP

Fully designed hardware IP block

Hardware Modeler

Historical solution that used real chips in the simulation process

IC Types

What are the types of integrated circuits?

IEEE 802.18-Radio Regulatory TAG

"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.

IEEE 802.3-Ethernet

IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.

Interconnects (BEOL)

Buses, NoCs and other forms of connection between various elements in an integrated circuit.

Internet of Things (IoT)

Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.

Interposers

Fast, low-power inter-die conduits for 2.5D electrical signals.

Ion Implants

Injection of critical dopants during the semiconductor manufacturing process.

IP-XACT

Standard for integration of IP in System-on-Chip

IR Drop

The voltage drop when current flows through a resistor.

Koomey’s Law

The energy efficiency of computers doubles roughly every 18 months.

Laws

Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.

Lint

Removal of non-portable or suspicious code

Lithography

Light used to transfer a pattern from a photomask onto a substrate.

Logic Simulation

A simulator is a software process used to execute a model of hardware

Machine Learning (ML)

An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.

Makimoto’s Wave

Observation related to the amount of custom and standard content in electronics.

Materials

Semiconductor materials enable electronic circuits to be constructed.

Memory

A semiconductor device capable of retaining state information for a defined period of time.

MEMS

Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.

Metcalfe’s Law

Observation that relates network value being proportional to the square of users

Metrology

Metrology is the science of measuring and characterizing tiny structures and materials.

Microcontroller (MCU)

A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.

Moore’s Law

Observation related to the growth of semiconductors by Gordon Moore.

Multi-Vt

Use of multi-threshold voltage devices

Nanosheet FET

A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.

Network on Chip (NoC)

An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.

Neural Networks

A method of collecting data from the physical world that mimics the human brain.

Nodes

Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.

Noise

Random fluctuations in voltage or current on a signal.

Non-Volatile Memory (NVM)

Memory in which information is retained even when a power source is not present.

Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1

NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and what’s being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.

Fundamentally, there are two types of NVM:

Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.

Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.

Then there’s the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, it’s difficult to do it because the oxide thickness is not there to do to make it happen.

However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.

The OTP technology doesn’t require the thicker oxide that is required for the MTP, and there is no floating gate.

1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/

Overlay

The ability of a lithography scanner to align and print various layers accurately on top of each other.

Packaging

How semiconductors get assembled and packaged.

Pellicle

A thin membrane that prevents a photomask from being contaminated.

Photomask

A template of what will be printed on a wafer.

Photoresist

Light-sensitive material used to form a pattern on the substrate.

Physical Design

Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.

Physical Layer (PHY)

Physically connects devices and is the conduit that encodes, decodes bits of data.

PODEM

An algorithm used ATPG

Portable Stimulus (PSS)

Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.

Power Gating

Reducing power by turning off parts of a design

Power Gating Retention

Special flop or latch used to retain the state of the cell when its main power supply is shut off.

Power Management IC (PMIC)

An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.

Power MOSFETs

A power semiconductor used to control and convert electric power.

Power Semiconductors

A power IC is used as a switch or rectifier in high voltage power applications.

Processors

An integrated circuit or part of an IC that does logic and math processing.

Reliability Verification

Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.

RISC-V

An open-source ISA used in designing integrated circuits at lower cost.

RTL Signoff

A series of requirements that must be met before moving past the RTL phase

RVM

Verification methodology based on Vera

Scan Test

Additional logic that connects registers into a shift register or scan chain for increased test efficiency.

Scoreboard

Mechanism for storing stimulus in testbench

Sensors

Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.

serializer/deserializer (SerDes)

A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.

Shift Left

In semiconductor development flow, tasks once performed sequentially must now be done concurrently.

Short Channel Effects

When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.

Side Channel Attacks

A class of attacks on a device and its contents by analyzing information using different access methods.

Simulation

A simulator exercises of model of hardware

SPICE

Circuit Simulator first developed in the 70s

Standards

Standards are important in any industry.

System on Chip (SoC)

A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor

SystemC

A class library built on top of the C++ language used for modeling hardware

SystemC-AMS

Analog and mixed-signal extensions to SystemC

Testbench

Software used to functionally verify a design

Transistors

Basic building block for both analog and digital integrated circuits.

Triple Patterning

A multi-patterning technique that will be required at 10nm and below.

Tunnel FET

A type of transistor under development that could replace finFETs in future process technologies.

Unified Coverage Interoperability Standard (Verification)

The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.