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Minor fix to d10v disassembler

Nick Clifton nickc@cygnus.com
Mon Nov 22 07:15:00 GMT 1999 
Hi Guys,

  In case anyone is interested I have checked in the following small
  patch so that the d10v-elf toolchain can correctly disassemble the
  "cpfg,f0,c" instruction.

Cheers
	Nick


1999-11-22  Nick Clifton  <nickc@cygnus.com>

	* d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction.

Index: opcodes/d10v-opc.c
===================================================================
RCS file: /cvs/cvsfiles/devo/opcodes/d10v-opc.c,v
retrieving revision 1.18
diff -p -r1.18 d10v-opc.c
*** d10v-opc.c	1999/09/12 15:16:39	1.18
--- d10v-opc.c	1999/11/22 15:06:13
*************** const struct d10v_opcode d10v_opcodes[] 
*** 206,213 ****
    { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
    { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
    { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
    { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
-   { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, CFSRC } },
    { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } },
    { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
    { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },
--- 206,213 ----
    { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
    { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
    { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
+   { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } },
    { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
    { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } },
    { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
    { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },
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