SSE x86-64 fix

Jan Hubicka jh@suse.cz
Tue Feb 6 15:51:00 GMT 2001
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Hi
This patch makes gas to accept 64bit versions of SSE converisons instructions.
If no one will cry, I will install it to both branches.

Wed Feb  7 00:47:11 CET 2001  Jan Hubicka  <jh@suse.cz>

	* i386.h (i386_optab): SSE integer converison instructions have
	64bit versions on x86-64.
	* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
	instructions.
	(putop): Handle 'Y'

Index: src/include/opcode/i386.h
===================================================================
RCS file: /cvs/src/src/include/opcode/i386.h,v
retrieving revision 1.26
diff -c -3 -p -r1.26 i386.h
*** i386.h	2001/01/24 07:32:34	1.26
--- i386.h	2001/02/06 23:41:28
*************** static const template i386_optab[] = {
*** 1112,1121 ****
  {"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
  {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
  {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, FP|Modrm,	{ Reg32|WordMem, RegXMM, 0 } },
! {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
  {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
  {"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
  {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
--- 1112,1121 ----
  {"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
  {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
  {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
! {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
  {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegXMM|WordMem, Reg32|Reg64, 0 } },
  {"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
  {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
*************** static const template i386_optab[] = {
*** 1212,1218 ****
  {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
  {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
  {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
! {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, FP|Modrm,	{ Reg32|LongMem, RegXMM, 0 } },
  {"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
  {"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
--- 1212,1218 ----
  {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
  {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
  {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
! {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
  {"divpd",     2, 0x660f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"divsd",     2, 0xf20f5e,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
  {"maxpd",     2, 0x660f5f,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
*************** static const template i386_optab[] = {
*** 1250,1260 ****
  {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, Reg32, 0 } },
  {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
  {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM, 0 } },
--- 1250,1260 ----
  {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
  {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
! {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
  {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
  {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM, 0 } },
Index: src/opcodes/i386-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i386-dis.c,v
retrieving revision 1.13.2.1
diff -c -3 -p -r1.13.2.1 i386-dis.c
*** i386-dis.c	2001/02/01 15:43:06	1.13.2.1
--- i386-dis.c	2001/02/06 23:41:36
*************** struct dis386 {
*** 439,444 ****
--- 439,445 ----
     'T' => print 'q' in 64bit mode and behave as 'I' otherwise
     'X' => print 's', 'd' depending on data16 prefix (for XMM)
     'W' => print 'b' or 'w' ("w" or "de" in intel mode)
+    'Y' => 'q' if instruction has an REX 64bit overwrite prefix
  */
  
  static const struct dis386 dis386_att[] = {
*************** static const struct dis386 prefix_user_t
*** 2578,2600 ****
    /* PREGRP2 */
    {
      { "cvtpi2ps", XM, EM, XX },
!     { "cvtsi2ss", XM, Ev, XX },
      { "cvtpi2pd", XM, EM, XX },
!     { "cvtsi2sd", XM, Ev, XX },
    },
    /* PREGRP3 */
    {
      { "cvtps2pi", MX, EX, XX },
!     { "cvtss2si", Gv, EX, XX },
      { "cvtpd2pi", MX, EX, XX },
!     { "cvtsd2si", Gv, EX, XX },
    },
    /* PREGRP4 */
    {
      { "cvttps2pi", MX, EX, XX },
!     { "cvttss2si", Gv, EX, XX },
      { "cvttpd2pi", MX, EX, XX },
!     { "cvttsd2si", Gv, EX, XX },
    },
    /* PREGRP5 */
    {
--- 2579,2601 ----
    /* PREGRP2 */
    {
      { "cvtpi2ps", XM, EM, XX },
!     { "cvtsi2ssY", XM, Ev, XX },
      { "cvtpi2pd", XM, EM, XX },
!     { "cvtsi2sdY", XM, Ev, XX },
    },
    /* PREGRP3 */
    {
      { "cvtps2pi", MX, EX, XX },
!     { "cvtss2siY", Gv, EX, XX },
      { "cvtpd2pi", MX, EX, XX },
!     { "cvtsd2siY", Gv, EX, XX },
    },
    /* PREGRP4 */
    {
      { "cvttps2pi", MX, EX, XX },
!     { "cvttss2siY", Gv, EX, XX },
      { "cvttpd2pi", MX, EX, XX },
!     { "cvttsd2siY", Gv, EX, XX },
    },
    /* PREGRP5 */
    {
*************** putop (template, sizeflag)
*** 3849,3854 ****
--- 3850,3864 ----
  	  else
  	    *obufp++ = 's';
            used_prefixes |= (prefixes & PREFIX_DATA);
+ 	  break;
+ 	case 'Y':
+           if (intel_syntax)
+             break;
+ 	  if (rex & REX_MODE64)
+ 	    {
+ 	      USED_REX (REX_MODE64);
+ 	      *obufp++ = 'q';
+ 	    }
  	  break;
  	  /* implicit operand size 'l' for i386 or 'q' for x86-64 */
  	case 'W':
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