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ARM as ... possible bug

Matthew Gretton-Dann matthew.gretton-dann@arm.com
Mon Dec 12 10:36:00 GMT 2011 
On 12/12/11 10:15, Dave Pawson wrote:
> Thanks for the explanation Matt.
>
> On 12 December 2011 09:27, Matthew Gretton-Dann
> <matthew.gretton-dann@arm.com>  wrote:
>> On 11/12/11 10:19, Dave Pawson wrote:
>>>
>>> strexd r0, r1,r2,[r4]
>>>
>>> produces
>>> arm.asm:275: Error: even register required -- `strexd r0,r1,r2,[r4]'
>>> failed, quitting
>
>> r1 in your example is the register producing the error.  In ARM state[1] the
>> first register transferred must be an even numbered register, and the second
>> register transferred must be the register numbered one higher.
>>
>> So   strexd r0, r2, r3, [r4] is valid
>> But  strexd r0, r2, r6, [r4] is not.
>>
>> The ARMARM describes this in the ARM state encoding specific operations (the
>> pseudo-code that goes with the ARM state encoding).
>
> <admission>I'm not very good with the p-code</admission>
>
> if ConditionPassed() then
> EncodingSpecificOperations(); NullCheckIfThumbEE(n);

EncodingSpecificOperations() means 'execute the pseudo-code that appears 
underneath the encoding bit pattern'.

So for ARM state strexd encoding this says that if the bottom bit of the 
first transfer register (Rt) is 1 then the instructions is 'UNPREDICTABLE'.

Take a look at the description for ldrexd where this is documented in a 
slightly clearer manner.

> address = R[n];
> // Create doubleword to store such that R[t] will be stored at address
> and R[t2] at address+4.
> value = if BigEndian() then R[t]:R[t2] else R[t2]:R[t];
> if ExclusiveMonitorsPass(address,8) then
> MemA[address,8] = value; R[d] = 0;
> else
> R[d] = 1;
>
> Sorry Matt, I see nothing there about Rt having to be even numbered?
> It's the sort of error that leaves me scratching my head and moaning
> about the documentation?
> It's quite confusing, appears to me unreasonable.
> I can deduce that the two registers must be consecutive (Rt2 not stored in
> the instruction) but I find the documentation sadly lacking on this
> (distinctly odd) restriction of use?

I hope this helps.

Thanks,

Matt

-- 
Matthew Gretton-Dann
Principal Engineer, PD Software - Tools, ARM Ltd
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