Mike Frysinger vapier@gentoo.org
Thu Mar 24 05:26:00 GMT 2011

• Previous message (by thread): gas: blackfin: test all 16bit insns
• Next message (by thread): [PATCH] gas: blackfin: reject invalid register destinations for vector add/sub
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

---

If the MAC1 part of the insn is disabled, then the (M) flag is ignored.
Rather than include it in the decode, move the MM clearing to the MAC0
portion of the code.

Committed.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
---
 opcodes/bfin-dis.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index 8970afd..fd51bee 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -3028,13 +3028,16 @@ decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 	{
 	  if (MM)
 	    OUTS (outf, " (M)");
-	  MM = 0;
 	  OUTS (outf, ", ");
 	}
     }
 
   if (w0 == 1 || op0 != 3)
     {
+      /* Clear MM option since it only matters for MAC1, and if we made
+         it this far, we've already shown it or we want to ignore it.  */
+      MM = 0;
+
       if (w0)
 	OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
 
-- 
1.7.4.1

---

• Previous message (by thread): gas: blackfin: test all 16bit insns
• Next message (by thread): [PATCH] gas: blackfin: reject invalid register destinations for vector add/sub
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

---

More information about the Binutils mailing list