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Fwd: [PATCH, ARM]An accurate way to calculate the target arch attribute

Richard Earnshaw rearnsha@arm.com
Wed Nov 19 10:15:00 GMT 2014 
On 29/09/14 04:10, Terry Guo wrote:
> Hi there,
> 
> When target isn't specified from either command line or .arch/.cpu
> directive, current gas will calculate the target arch before
> relaxation step and assume that a possible relaxation will happen
> anyway even this relaxation doesn't happen in late relaxation step.
> This causes a overly assumption to target arch e.g. set target arch to
> armv6t2 where armv4t is good enough.
> 
> The attached patch intends to do an accurate calculation of target
> arch by considering the target arch in relaxation step.
> 
> Tested with Binutils regression test. Is it OK?
> 
> BR,
> Terry
> 
> gas/
> 2014-09-29  Terry Guo  <terry.guo@arm.com>
> 
>           * config/tc-arm.c (md_assemble): Do not consider relaxation.
>           (md_convert_frag): Test and set target arch attribute accordingly.
>           (aeabi_set_attribute_string): Turn it into a global function.
>           * config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
>           (aeabi_set_public_attributes): Declare it.
> 
> gas/testsuite/
> 2014-09-29  Terry Guo  <terry.guo@arm.com>
> 
>           * gas/arm/attr-arch-assumption.d: New file.
>           * gas/arm/attr-arch-assumption.s: Likewise.
> 

These bits seem essentially OK, but ...

> ld/testsuite/
> 2014-09-29  Terry Guo  <terry.guo@arm.com>
> 
>           * ld-arm/tls-longplt-lib.d: Updated.
>           * ld-arm/tls-longplt-lib.s: Likewise.
>           * ld-arm/tls-longplt.d: Likewise.
>           * ld-arm/tls-longplt.s: Likewise.

Why is this needed?  This code doesn't look like it needs to assume v6t2
as a baseline.

R.

> 
> 
> arm-attr-sec-relaxation-v1.txt
> 
> 
> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
> index 5077f87..a79e383 100644
> --- a/gas/config/tc-arm.c
> +++ b/gas/config/tc-arm.c
> @@ -17672,9 +17672,9 @@ md_assemble (char *str)
>        /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
>  	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
>  	 anything other than bl/blx and v6-M instructions.
> -	 This is overly pessimistic for relaxable instructions.  */
> -      if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
> -	   || inst.relax)
> +	 The impact of relaxable instructions will be considered later after we
> +	 finish all relaxation.  */
> +      if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
>  	  && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
>  	       || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
>  	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
> @@ -20508,6 +20508,11 @@ md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
>    fixp->fx_file = fragp->fr_file;
>    fixp->fx_line = fragp->fr_line;
>    fragp->fr_fix += fragp->fr_var;
> +
> +  /* Set whether we use thumb-2 ISA based on final relaxation results.  */
> +  if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
> +      && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
> +    ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
>  }
>  
>  /* Return the size of a relaxable immediate operand instruction.
> @@ -25091,7 +25096,7 @@ aeabi_set_attribute_string (int tag, const char *value)
>  }
>  
>  /* Set the public EABI object attributes.  */
> -static void
> +void
>  aeabi_set_public_attributes (void)
>  {
>    int arch;
> diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
> index a7a0cd0..e5d67b3 100644
> --- a/gas/config/tc-arm.h
> +++ b/gas/config/tc-arm.h
> @@ -116,6 +116,9 @@ extern bfd_boolean tc_start_label_without_colon (char, const char *);
>  #define md_end arm_md_end
>  extern void arm_md_end (void);
>  bfd_boolean arm_is_eabi (void);
> +
> +#define md_post_relax_hook		aeabi_set_public_attributes ()
> +extern void aeabi_set_public_attributes (void);
>  #endif
>  
>  /* NOTE: The fake label creation in stabs.c:s_stab_generic() has
> diff --git a/gas/testsuite/gas/arm/attr-arch-assumption.d b/gas/testsuite/gas/arm/attr-arch-assumption.d
> new file mode 100644
> index 0000000..e5f60b0
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/attr-arch-assumption.d
> @@ -0,0 +1,11 @@
> +# name: arch and isa entries in elf attribute section
> +# source: attr-arch-assumption.s
> +# as:
> +# readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi* *-*-nacl*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_arch: v4T
> +  Tag_THUMB_ISA_use: Thumb-1
> diff --git a/gas/testsuite/gas/arm/attr-arch-assumption.s b/gas/testsuite/gas/arm/attr-arch-assumption.s
> new file mode 100644
> index 0000000..b5b9460
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/attr-arch-assumption.s
> @@ -0,0 +1,5 @@
> +	.syntax unified
> +	.thumb
> +foo:
> +	cmp r0, r1
> +	beq foo
> diff --git a/ld/testsuite/ld-arm/tls-longplt-lib.d b/ld/testsuite/ld-arm/tls-longplt-lib.d
> index 2c81fbe..97aaad8 100644
> --- a/ld/testsuite/ld-arm/tls-longplt-lib.d
> +++ b/ld/testsuite/ld-arm/tls-longplt-lib.d
> @@ -32,7 +32,7 @@ Disassembly of section .text:
>      81e4:	000080b4 	.word	0x000080b4
>      81e8:	4801      	ldr	r0, \[pc, #4\]	; .*
>      81ea:	f7ff efe0 	blx	81ac <.*>
> -    81ee:	46c0      	nop			; .*
> +    81ee:	bf00      	nop
>      81f0:	000080a5 	.word	0x000080a5
>  
>  Disassembly of section .foo:
> @@ -48,7 +48,7 @@ Disassembly of section .foo:
>   400101c:	fc00f284 	.word	0xfc00f284
>   4001020:	4801      	ldr	r0, \[pc, #4\]	; .*
>   4001022:	f000 e806 	blx	4001030 .*
> - 4001026:	46c0      	nop			; .*
> + 4001026:	bf00      	nop
>   4001028:	fc00f26d 	.word	0xfc00f26d
>   400102c:	00000000 	.word	0x00000000
>  
> diff --git a/ld/testsuite/ld-arm/tls-longplt-lib.s b/ld/testsuite/ld-arm/tls-longplt-lib.s
> index e0650cb..8cdfe27 100644
> --- a/ld/testsuite/ld-arm/tls-longplt-lib.s
> +++ b/ld/testsuite/ld-arm/tls-longplt-lib.s
> @@ -1,4 +1,5 @@
>  	.syntax unified
> +	.arch armv6t2
>  	.text
>  text:
>  	.arm
> diff --git a/ld/testsuite/ld-arm/tls-longplt.d b/ld/testsuite/ld-arm/tls-longplt.d
> index 175c561..afa6b06 100644
> --- a/ld/testsuite/ld-arm/tls-longplt.d
> +++ b/ld/testsuite/ld-arm/tls-longplt.d
> @@ -32,7 +32,7 @@ Disassembly of section .text:
>      81e8:	000080d4 	.word	0x000080d4
>      81ec:	4801      	ldr	r0, \[pc, #4\]	; .*
>      81ee:	f7ff efe0 	blx	81b0 .*
> -    81f2:	46c0      	nop			; .*
> +    81f2:	bf00      	nop
>      81f4:	000080c5 	.word	0x000080c5
>  
>  Disassembly of section .foo:
> @@ -48,7 +48,7 @@ Disassembly of section .foo:
>   400101c:	fc00f2a0 	.word	0xfc00f2a0
>   4001020:	4801      	ldr	r0, \[pc, #4\]	; .*
>   4001022:	f000 f809 	bl	4001038 .*
> - 4001026:	46c0      	nop			; .*
> + 4001026:	bf00      	nop
>   4001028:	fc00f291 	.word	0xfc00f291
>   400102c:	00000000 	.word	0x00000000
>  
> diff --git a/ld/testsuite/ld-arm/tls-longplt.s b/ld/testsuite/ld-arm/tls-longplt.s
> index 42eea19..37d166f 100644
> --- a/ld/testsuite/ld-arm/tls-longplt.s
> +++ b/ld/testsuite/ld-arm/tls-longplt.s
> @@ -1,4 +1,5 @@
>  	.syntax unified
> +	.arch armv6t2
>  	.text
>  text:
>  	.arm
>
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