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[PATCH 7/9] gas, opcodes: SPARC M7 support: %mwait ancillary state register and associated instructions.

Jose E. Marchesi jose.marchesi@oracle.com
Thu Oct 2 16:15:00 GMT 2014 
The OSA2015 specification introduces a new ancillary state register
(%asr28) called %mwait.  This register can be written and read using
the rdasr|wrasr instructions while providing an ASR field of 28.
Additionally the new instruction MWAIT can also be used to write to
the %mwait register.

This patch adds support to opcodes and gas for the %mwait ancillary
state register and the following instructions:

- mwait
- wr r,r,%mwait
- wr r,i,%mwait
- rd %mwait,r

Tested in sparc64-unknown-linux-gnu.

gas/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (v9a_asr_table): Add the %mwait (%asr28)
	ancillary state register to the table.

gas/testsuite/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/sparc.exp (sparc_elf_setup): Run the mwait test.

	* gas/sparc/mwait.d: New file.
	* gas/sparc/mwait.s: Likewise.

opcodes/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
	ancillary state register to the table.

	* sparc-opc.c (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait',
	`wr r,i,%mwait' and `rd %mwait,r' instructions.
---
 gas/ChangeLog                     |    5 +++++
 gas/config/tc-sparc.c             |    1 +
 gas/testsuite/ChangeLog           |    7 +++++++
 gas/testsuite/gas/sparc/mwait.d   |   13 +++++++++++++
 gas/testsuite/gas/sparc/mwait.s   |    7 +++++++
 gas/testsuite/gas/sparc/sparc.exp |    1 +
 opcodes/ChangeLog                 |    8 ++++++++
 opcodes/sparc-dis.c               |    2 +-
 opcodes/sparc-opc.c               |    7 +++++++
 9 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/sparc/mwait.d
 create mode 100644 gas/testsuite/gas/sparc/mwait.s

diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 852ee36..7af5911 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -839,6 +839,7 @@ struct priv_reg_entry v9a_asr_table[] =
   {"pause", 27},
   {"pic", 17},
   {"pcr", 16},
+  {"mwait", 28},
   {"gsr", 19},
   {"dcr", 18},
   {"cfr", 26},
diff --git a/gas/testsuite/gas/sparc/mwait.d b/gas/testsuite/gas/sparc/mwait.d
new file mode 100644
index 0000000..0571b52
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.d
@@ -0,0 +1,13 @@
+#as: -Av9x
+#objdump: -dr
+#name: sparc OSA2015 %mwait asr and MWAIT instruction
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	83 47 00 00 	rd  %mwait, %g1
+   4:	b9 80 a0 03 	wr  %g2, 3, %mwait
+   8:	b9 80 00 01 	mwait  %g1
+   c:	b9 80 20 03 	mwait  3
diff --git a/gas/testsuite/gas/sparc/mwait.s b/gas/testsuite/gas/sparc/mwait.s
new file mode 100644
index 0000000..0379746
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mwait.s
@@ -0,0 +1,7 @@
+# Test reads/writes to the %mwait asr register and the MWAIT
+# instruction
+	.text
+	rd	%mwait, %g1
+	wr	%g2, 0x3, %mwait
+	mwait	%g1
+	mwait	0x3
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index ed23655..c7d99a9 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -90,6 +90,7 @@ if [istarget sparc*-*-*] {
     run_dump_test "ld_st_fsr"
     run_dump_test "edge"
     run_dump_test "flush"
+    run_dump_test "mwait"
 
     run_list_test "pr4587" ""
 }
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index db09c44..49a16c2 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -106,7 +106,7 @@ static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
   "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
-  "pause", "cps"
+  "pause", "mwait"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 8c3251a..ba1ea25 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -863,6 +863,7 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "tst",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0),	"2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
 { "tst",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),	"1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */
 
+
 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|ASI(~0),		"1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */
 { "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1),			"1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */
 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),	"2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
@@ -925,6 +926,8 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "wr", F3(2, 0x30, 1)|RD(26),	F3(~2, ~0x30, ~1)|RD(~26),		"1,i,_", 0, HWCAP_CBCOND, 0, v9b }, /* wr r,i,%cfr */
 { "wr", F3(2, 0x30, 0)|RD(27),	F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0),	"1,2,_", 0, HWCAP_PAUSE, 0, v9b }, /* wr r,r,%pause */
 { "wr", F3(2, 0x30, 1)|RD(27),	F3(~2, ~0x30, ~1)|RD(~27),		"1,i,_", 0, HWCAP_PAUSE, 0, v9b }, /* wr r,i,%pause */
+{ "wr",    F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, 0, HWCAP2_MWAIT, v9b }, /* wr r,r,%mwait */
+{ "wr", F3(2, 0x30, 1)|RD(28),	F3(~2, ~0x30, ~1)|RD(~28),		"1,i,_", 0, 0, HWCAP2_MWAIT, v9b }, /* wr r,i,%mwait */
 
 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9b }, /* wr %g0,i,%pause */
 
@@ -949,6 +952,7 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "rd",	F3(2, 0x28, 0)|RS1(24),		F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),	"/,d", 0, HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */
 { "rd",	F3(2, 0x28, 0)|RS1(25),		F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),	"/,d", 0, HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */
 { "rd",	F3(2, 0x28, 0)|RS1(26),		F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),	"/,d", 0, HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */
+{ "rd",	F3(2, 0x28, 0)|RS1(28),		F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0),	"/,d", 0, 0, HWCAP2_MWAIT, v9b }, /* rd %mwait,r */
 
 { "rdpr",	F3(2, 0x2a, 0),		F3(~2, ~0x2a, ~0)|SIMM13(~0),	"?,d", 0, 0, 0, v9 },   /* rdpr %priv,r */
 { "wrpr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0),		"1,2,!", 0, 0, 0, v9 }, /* wrpr r1,r2,%priv */
@@ -2048,6 +2052,9 @@ SLCBCC("cbnefr", 15),
 { "flcmpd",	CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
 { "flcmpd",	CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, 0, v9b },
 
+{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0),  "2", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait r */
+{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait imm */
+
 /* More v9 specific insns, these need to come last so they do not clash
    with v9a instructions such as "edge8" which looks like impdep1. */
 
-- 
1.7.10.4
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