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[committed, PATCH] Remove Disp16|Disp32 from 64-bit direct branches

H.J. Lu hjl.tools@gmail.com
Wed May 13 13:15:00 GMT 2015 
On Wed, May 13, 2015 at 5:27 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 13.05.15 at 13:35, <hjl.tools@gmail.com> wrote:
>> On Tue, May 12, 2015 at 11:18 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>> What _works_ on Intel processors is secondary here. Fact is that
>>> the x86-64 design came from AMD, and hence Intel CPUs doing
>>> things differently than AMD's is - be honest - a flaw. The more
>>
>> I don't think who came first is relevant here.  What relevant are
>>
>> 1. AMD and Intel specs are different.
>
> Very interesting statement. If you want to stick to what Intel
> specifies, then look at the "N.S." of the respective CALL/JMP
> encodings. The explanation of N.S. specifically says "Using an
> address override prefix in 64-bit mode may result in model-
> specific execution behavior." I don't think you want the
> assembler to behave in model-specific ways.

Intel SDM says

A relative offset (rel16 or rel32) is generally specified as a label
in assembly code. But at the machine code level, it
is encoded as a signed, 16- or 32-bit immediate value. This value is
added to the value in the EIP(RIP) register. In
64-bit mode the relative offset is always a 32-bit immediate value
which is sign extended to 64-bits before it is
added to the value in the RIP register for the target calculation. As
with absolute offsets, the operand-size attribute
determines the size of the target operand (16, 32, or 64 bits). In
64-bit mode the target operand will always be 64-
bits because the operand size is forced to 64-bits for near branches.A
relative offset (rel16 or rel32) is generally specified as a label in
assembly code. But at the machine code level, it
is encoded as a signed, 16- or 32-bit immediate value. This value is
added to the value in the EIP(RIP) register. In
64-bit mode the relative offset is always a 32-bit immediate value
which is sign extended to 64-bits before it is
added to the value in the RIP register for the target calculation. As
with absolute offsets, the operand-size attribute
determines the size of the target operand (16, 32, or 64 bits). In
64-bit mode the target operand will always be 64-
bits because the operand size is forced to 64-bits for near branches.

It is always 64-bit in 64-bit mode on Intel processors.

> And again - Intel's treatment is inconsistent (operand size prefix
> meaning different things depending on context), while AMD's is
> consistent.

This isn't a good situation and I can't find a good compromise.
I am open to all suggestions.

-- 
H.J.
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