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[PATCH 1/3] opcodes/arc: Compute insn lengths in disassembler

Claudiu Zissulescu Claudiu.Zissulescu@synopsys.com
Tue Apr 12 09:27:00 GMT 2016 
Hi Andrew,
 
> The table is self-checking while being built, it only contains the
> instructions for the current architecture being disassembled, and if
> different instructions with the same major opcode have different
> lengths, this will cause an error while the table is being filled.

I still have some questions regarding your newly proposed way of decoding the instructions. What bothers me is the fact you relay on the existing encodings, but what is happening when we have extension instructions. For ARCompact the extension instructions may  start from major 0x05 and end somewhere at 0x0B, For ARCv2 the extension instructions start from 0x05 and ends at 0x07. The official docs are stipulating those ones are 32-bit. Though, I've seen custom instructions defined as short instructions(16-bit). How your proposed patch is addressing the extension instructions (let us not take into account the short ones)?

As far as I can see, we can actually say that all major larger than 0x0B for ARCompact are 16-bit, and all major larger than 0x07 for ARCv2 are 16-bit. Though some sanity testing needs to be done.

Name conventions:
MAJOR		Notes
0x04 		ARC 32-bit basecase instructions;
0x05 - 0x06 	ARC 32-bit extension instructions;
0x07		User 32-bit extension instructions;
0x08		ARCompact: User 32-bit extension instructions; ARCv2: 16-bit instructions
0x09		ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions
0x0A		ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions
0x0B		ARCompact: Market-specific extension instructions; ARCv2: 16-bit instructions

Thanks,
Claudiu
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