Renlin Li renlin.li@foss.arm.com
Fri Feb 19 11:24:00 GMT 2016

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Hi all,

This is a patch to add fp16 instruction dissembler support for armv8.2.

For AArch32 Scalar floating-point, a new set of scalar data processing instructions are added
using Coprocessor9 for half-precision calculations or conversions.

For all of these instructions being added, having the cond field as anything other than 1110 is
UNPREDICTABLE. The behavior is not guaranteed.

To be specific, the following instructions are added.

New VMOVX and VINS instructions are added to allow the extraction and insertion of the
upper 16 bits of a 32-bit vector register.
vins.f16
vmovx.f16

vabs.f16
vadd.f16
vcmp.f16
vcmpe.f16

VCVT (between floating-point and fixed-point)
vcvt.f16.s32
vcvt.f16.u32
vcvt.s32.f16
vcvt.u32.f16

VCVT (between floating-point and integer, both directions)
vcvt.s32.f16
vcvt.u32.f16
vcvt.f16.u32
vcvt.f16.s32

vcvta.u32.f16
vcvta.s32.f16
vcvtm.u32.f16
vcvtm.s32.f16
vcvtn.u32.f16
vcvtn.s32.f16
vcvtp.u32.f16
vcvtp.s32.f16
vcvtr.u32.f16
vcvtr.s32.f16
  
vdiv.f16
vfma.f16
vfms.f16
vfnma.f16
vfnms.f16
vmaxnm.f16
vminnm.f16
fmla.f16
vmls.f16

VMOV(between general-purpose register and half-precision register, immediate)
vmov.f16
vmov.f16

vmul.f16
vneg.f16
vnmla.f16
vnmls.f16
vnmul.f16

vrinta.f16
vrintm.f16
vrintn.f16
vrintp.f16
vrintr.f16
vrintx.f16
vrintz.f16

vseleq.f16
vselge.f16
vselgt.f16
vselvs.f16

vsqrt.f16
vsub.f16

load/store literal or address from register with optional offset
vldr.16
vstr.16

  
Binutils, gas, ld checked Okay without any issues. Okay to commit?

opcodes/ChangeLog:
   	  	
2016-02-19  Renlin Li  <renlin.li@arm.com>

         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
	(print_insn_coprocessor): Support fp16 instruction.	  	

gas/ChangeLog:
2016-02-19  Renlin Li  <renlin.li@arm.com>

         * testsuite/gas/arm/copro.d: Adjust output.
         * testsuite/gas/arm/copro.s: Adjust co-processor num.

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