[PATCH] MIPS: Correct opcode for some IL3A instructions
Jiaxun Yang
jiaxun.yang@flygoat.com
Wed Jan 24 09:18:00 GMT 2018
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Wed Jan 24 09:18:00 GMT 2018
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Correct instrotions' opcode according to Loongson 3A2000's user manual. Ref(in Chinese): http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf ChangeLog: opcodes/ * mips-opc.c (mips_opcodes): Fix opcodes gslwlec1, gslwgtc1, gsldlec1, gsldgtc1. --- opcodes/mips-opc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 180d613c93..248aab5124 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -470,10 +470,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, -{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, -{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, -{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, -{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwlec1", "T,b,d", 0xc800001c, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwgtc1", "T,b,d", 0xc800001d, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldlec1", "T,b,d", 0xc800001e, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldgtc1", "T,b,d", 0xc800001f, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, -- 2.16.0
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