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[PATCH] x86/Intel: accept memory operand size specifiers for CET insns

H.J. Lu hjl.tools@gmail.com
Tue Jul 10 14:50:00 GMT 2018 
On Tue, Jul 10, 2018 at 7:12 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 10.07.18 at 15:59, <hjl.tools@gmail.com> wrote:
>> On Tue, Jul 10, 2018 at 6:33 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> gas/
>>> 2018-07-10  Jan Beulich  <jbeulich@suse.com>
>>>
>>>         * testsuite/gas/i386/cet.s, testsuite/gas/i386/x86-64-cet.s:
>>>         Add Intel cases with operand size specifiers.
>>>         * testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
>>>         testsuite/gas/i386/x86-64-cet-intel.d,
>>>         testsuite/gas/i386/x86-64-cet.d: Adjust expectations.
>>>
>>> opcodes/
>>> 2018-07-10  Jan Beulich  <jbeulich@suse.com>
>>>
>>>         * i386-opc.tbl (wrssd, wrussd): Add Dword.
>>>         (wrssq, wrussq): Add Qword.
>>>         * i386-tbl.h: Re-generate.
>>>
>>
>> Should the disassembler be updated to add DWORD/QWORD?
>
> I generally think this disassembler is way to chatty with these
> operand sizes in Intel syntax mode. Since the (sort of) suffixes
> already clarify operand size (odd enough - WRSS and WRUSS
> would have been quite fine as uniform mnemonics), I'd prefer to
> not add any. I also don't really expect humans to use them in
> assembly code, but machine generated assembly code could
> easily produce them uniformly everywhere (I didn't check how
> gcc avoids doing so, or whether it's simply broken right now).
>

Patch is OK then.

Thanks.

-- 
H.J.
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