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[PATCH 3/3] Enable Intel MOVDIRI, MOVDIR64B instructions.

H.J. Lu hjl.tools@gmail.com
Wed May 9 18:18:00 GMT 2018 
On Tue, May 8, 2018 at 11:41 PM, Jan Beulich <jbeulich@suse.com> wrote:
>>>> "H.J. Lu" <hjl.tools@gmail.com> 05/07/18 7:55 PM >>>
>>On Thu, Apr 26, 2018 at 11:40 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>>> On 26.04.18 at 21:49, <igor.v.tsimbalist@intel.com> wrote:
>>>>+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg16|Reg32 }
>>>>+movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|ZMMword|BaseIndex|Disp8|Disp32|Disp32S, Reg32|Reg64 }
>>>
>>> Almost all the same here. Additionally, while I can see that ZMMword fits
>>> the 64-byte operand size, I really think it would look rather odd to have
>>> "zmmword ptr" used on an operand here. Simply require no operand size
>>> prefix (in Intel syntax mode), just like you make the disassembler not
>>> produce any?
>>
>>Fixed.  We need 2 templates since Reg16 isn't supported in 64-bit mode.
>
> Well, yes, with the current code in tc-i386.c this is unavoidable. I have a
> respective item on my todo list already, since it would also help SVM insns
> (which currently wrongly disallow Reg16) without having to duplicate their
> templates.
>
> In any event - please drop the now redundant Disp<N> from all three templates.
>

This is what I checked in.

Thanks.

-- 
H.J.
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