Home Original page

[PATCH 1/2] Arm64: correct "sha3" arch-extension directive handling

Jan Beulich jbeulich@suse.com
Mon Nov 25 09:40:00 GMT 2019 
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the
latter should not also disable the former.

In the course of adding respective tests also do away with the
duplication of crypto.d's contents in crypto-directive.d.

gas/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-aarch64.c (aarch64_features): Make SHA2 a prereq of
	SHA3.
	* testsuite/gas/aarch64/crypto.s
	* testsuite/gas/aarch64/crypto-directive.d: Refer to crypto.d
	for actual output.
	* testsuite/gas/aarch64/illegal-crypto-nofp.l: Relax
	expectations.
	* testsuite/gas/aarch64/crypto-directive2.d,
	testsuite/gas/aarch64/crypto-directive3.d: New.

--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8980,9 +8980,8 @@ static const struct aarch64_option_cpu_v
 			AARCH64_ARCH_NONE},
   {"sm4",		AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
 			AARCH64_ARCH_NONE},
-  {"sha3",		AARCH64_FEATURE (AARCH64_FEATURE_SHA2
-					 | AARCH64_FEATURE_SHA3, 0),
-			AARCH64_ARCH_NONE},
+  {"sha3",		AARCH64_FEATURE (AARCH64_FEATURE_SHA3, 0),
+			AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0)},
   {"rng",		AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
 			AARCH64_ARCH_NONE},
   {"ssbs",		AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
--- a/gas/testsuite/gas/aarch64/crypto-directive.d
+++ b/gas/testsuite/gas/aarch64/crypto-directive.d
@@ -1,27 +1,4 @@
 #objdump: -dr
 #as: --defsym DIRECTIVE=1
 #source: crypto.s
-
-.*:     file format .*
-
-Disassembly of section \.text:
-
-0+ <.*>:
-   0:	4e284be7 	aese	v7.16b, v31.16b
-   4:	4e285be7 	aesd	v7.16b, v31.16b
-   8:	4e286be7 	aesmc	v7.16b, v31.16b
-   c:	4e287be7 	aesimc	v7.16b, v31.16b
-  10:	5e280be7 	sha1h	s7, s31
-  14:	5e281be7 	sha1su1	v7.4s, v31.4s
-  18:	5e282be7 	sha256su0	v7.4s, v31.4s
-  1c:	5e1f01e7 	sha1c	q7, s15, v31.4s
-  20:	5e1f11e7 	sha1p	q7, s15, v31.4s
-  24:	5e1f21e7 	sha1m	q7, s15, v31.4s
-  28:	5e1f31e7 	sha1su0	v7.4s, v15.4s, v31.4s
-  2c:	5e1f41e7 	sha256h	q7, q15, v31.4s
-  30:	5e1f51e7 	sha256h2	q7, q15, v31.4s
-  34:	5e1f61e7 	sha256su1	v7.4s, v15.4s, v31.4s
-  38:	0e3fe1e7 	pmull	v7.8h, v15.8b, v31.8b
-  3c:	0effe1e7 	pmull	v7.1q, v15.1d, v31.1d
-  40:	4e3fe1e7 	pmull2	v7.8h, v15.16b, v31.16b
-  44:	4effe1e7 	pmull2	v7.1q, v15.2d, v31.2d
+#dump: crypto.d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/crypto-directive2.d
@@ -0,0 +1,4 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=2
+#source: crypto.s
+#dump: crypto.d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/crypto-directive3.d
@@ -0,0 +1,4 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=3
+#source: crypto.s
+#dump: crypto.d
--- a/gas/testsuite/gas/aarch64/crypto.s
+++ b/gas/testsuite/gas/aarch64/crypto.s
@@ -21,8 +21,16 @@
 
 	.text
 	.ifdef DIRECTIVE
+	.if DIRECTIVE > 1
+	.arch_extension aes
+	.arch_extension sha2
+	.else
 	.arch_extension crypto
 	.endif
+	.if DIRECTIVE == 3
+	.arch_extension nosha3
+	.endif
+	.endif
 
 	aese	v7.16b, v31.16b
 	aesd	v7.16b, v31.16b
--- a/gas/testsuite/gas/aarch64/illegal-crypto-nofp.l
+++ b/gas/testsuite/gas/aarch64/illegal-crypto-nofp.l
@@ -1,19 +1,19 @@
 [^:]*: Assembler messages:
-[^:]+:27: Error: selected processor does not support `aese v7\.16b,v31\.16b'
-[^:]+:28: Error: selected processor does not support `aesd v7\.16b,v31\.16b'
-[^:]+:29: Error: selected processor does not support `aesmc v7\.16b,v31\.16b'
-[^:]+:30: Error: selected processor does not support `aesimc v7\.16b,v31\.16b'
-[^:]+:32: Error: selected processor does not support `sha1h s7,s31'
-[^:]+:33: Error: selected processor does not support `sha1su1 v7\.4s,v31\.4s'
-[^:]+:34: Error: selected processor does not support `sha256su0 v7\.4s,v31\.4s'
-[^:]+:36: Error: selected processor does not support `sha1c q7,s15,v31\.4s'
-[^:]+:37: Error: selected processor does not support `sha1p q7,s15,v31\.4s'
-[^:]+:38: Error: selected processor does not support `sha1m q7,s15,v31\.4s'
-[^:]+:40: Error: selected processor does not support `sha1su0 v7\.4s,v15\.4s,v31\.4s'
-[^:]+:41: Error: selected processor does not support `sha256h q7,q15,v31\.4s'
-[^:]+:42: Error: selected processor does not support `sha256h2 q7,q15,v31\.4s'
-[^:]+:43: Error: selected processor does not support `sha256su1 v7\.4s,v15\.4s,v31\.4s'
-[^:]+:45: Error: selected processor does not support `pmull v7\.8h,v15\.8b,v31\.8b'
-[^:]+:46: Error: selected processor does not support `pmull v7\.1q,v15\.1d,v31\.1d'
-[^:]+:47: Error: selected processor does not support `pmull2 v7\.8h,v15\.16b,v31\.16b'
-[^:]+:48: Error: selected processor does not support `pmull2 v7\.1q,v15\.2d,v31\.2d'
+[^:]+:[0-9]+: Error: selected processor does not support `aese v7\.16b,v31\.16b'
+[^:]+:[0-9]+: Error: selected processor does not support `aesd v7\.16b,v31\.16b'
+[^:]+:[0-9]+: Error: selected processor does not support `aesmc v7\.16b,v31\.16b'
+[^:]+:[0-9]+: Error: selected processor does not support `aesimc v7\.16b,v31\.16b'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1h s7,s31'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1su1 v7\.4s,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha256su0 v7\.4s,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1c q7,s15,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1p q7,s15,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1m q7,s15,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha1su0 v7\.4s,v15\.4s,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha256h q7,q15,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha256h2 q7,q15,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `sha256su1 v7\.4s,v15\.4s,v31\.4s'
+[^:]+:[0-9]+: Error: selected processor does not support `pmull v7\.8h,v15\.8b,v31\.8b'
+[^:]+:[0-9]+: Error: selected processor does not support `pmull v7\.1q,v15\.1d,v31\.1d'
+[^:]+:[0-9]+: Error: selected processor does not support `pmull2 v7\.8h,v15\.16b,v31\.16b'
+[^:]+:[0-9]+: Error: selected processor does not support `pmull2 v7\.1q,v15\.2d,v31\.2d'
More information about the Binutils mailing list