[PATCH 2/3] RISC-V: Add instructions and operand set for z[fdq]inx

Nelson Chu nelson.chu@sifive.com
Tue Nov 9 09:51:55 GMT 2021
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This patch should work for zfinx.  But we need to add a new operand
'x', and add multiple extra entries of riscv_opcodes.  Jim has
suggested before, and after discussing with Kito, I think the better
solution should be as follows:

* Just change the zfinx instructions from INSN_CLASS_F to
INSN_CLASS_ZFINX class (or probably INSN_CLASS_F_OR_ZFINX), but keep
the original operands.  And then update the
riscv_multi_subset_supports,

@@ -287,6 +287,8 @@ riscv_multi_subset_supports (enum riscv_insn_class
insn_class)
       return riscv_subset_supports ("zbc");
     case INSN_CLASS_ZBS:
       return riscv_subset_supports ("zbs");
+    case INSN_CLASS_F_OR_ZFINX:
+      return (riscv_subset_supports ("f") || riscv_subset_supports ("zfinx"));
     default:
       as_fatal ("internal: unreachable");
       return false;

* In gas/config/tc-riscv.c:riscv_ip,

@@ -2530,7 +2532,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
expressionS *imm_expr,
            case 'T': /* Floating point RS2.  */
            case 'U': /* Floating point RS1 and RS2.  */
            case 'R': /* Floating point RS3.  */
-             if (reg_lookup (&asarg, RCLASS_FPR, &regno))
+             if (reg_lookup (&asarg, (riscv_subset_supports ("zfinx")
+                                      ? RCLASS_GPR : RCLASS_FPR), &regno))
                {
                  char c = *oparg;
                  if (*asarg == ' ')

Therefore, I can get the expected results as follows,

nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
        fadd.s fa0, fa1, fa2
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: illegal operands `fadd.s fa0,fa1,fa2'
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?

nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
        fadd.s a0, a1, a2
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: illegal operands `fadd.s a0,a1,a2'

nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
        flw     fa0, foo, a1
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: unrecognized opcode `flw fa0,foo,a1'
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?

Note that the error of flw is "unrecognized opcode", since we are
using INSN_CLASS_F for these non-zfinx instructions, and f cannot be
used with zfinx at the same time.  And fortunately, we only need to
hack this check for U, S, T, ... floating operand in the riscv_ip, we
don't need to handle them in the macro_build.

Thanks
Nelson



On Fri, Oct 29, 2021 at 12:50 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
>  gas/config/tc-riscv.c |  11 +++-
>  opcodes/riscv-opc.c   | 146 ++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 154 insertions(+), 3 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 2c4df208664..b879bf1ea8b 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1158,6 +1158,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>         USE_BITS (OP_MASK_RS1, OP_SH_RS1);
>         /* Fall through.  */
>        case 'T': /* RS2, floating point.  */
> +      case 'x': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* Fall through.  */
>        case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
>        case 'R': /* RS3, floating point.  */
>        case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
> @@ -2508,6 +2509,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>             case 'd': /* Destination register.  */
>             case 's': /* Source register.  */
>             case 't': /* Target register.  */
> +           case 'x': /* rs1 and rs2.  */
>             case 'r': /* RS3 */
>               if (reg_lookup (&s, RCLASS_GPR, &regno))
>                 {
> @@ -2519,12 +2521,15 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>                      string to figure out where it goes in the instruction.  */
>                   switch (c)
>                     {
> +        case 'd':
> +                     INSERT_OPERAND (RD, *ip, regno);
> +                     break;
>                     case 's':
>                       INSERT_OPERAND (RS1, *ip, regno);
>                       break;
> -                   case 'd':
> -                     INSERT_OPERAND (RD, *ip, regno);
> -                     break;
> +        case 'x':
> +                     INSERT_OPERAND (RS1, *ip, regno);
> +          /* fallthru */
>                     case 't':
>                       INSERT_OPERAND (RS2, *ip, regno);
>                       break;
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index b756bae64ab..435fb434161 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -534,52 +534,99 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
>  {"fmv.s",      0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fneg.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.s",     0, INSN_CLASS_ZFINX,   "d,x",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fabs.s",     0, INSN_CLASS_F,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.s",     0, INSN_CLASS_ZFINX,   "d,x",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fsgnj.s",    0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
> +{"fsgnj.s",    0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
>  {"fsgnjn.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
> +{"fsgnjn.s",   0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
>  {"fsgnjx.s",   0, INSN_CLASS_F,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
> +{"fsgnjx.s",   0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
>  {"fadd.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
>  {"fadd.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
> +{"fadd.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
> +{"fadd.s",     0, INSN_CLASS_ZFINX,   "d,s,t,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
>  {"fsub.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
>  {"fsub.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
> +{"fsub.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
> +{"fsub.s",     0, INSN_CLASS_ZFINX,   "d,s,t,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
>  {"fmul.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
>  {"fmul.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
> +{"fmul.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
> +{"fmul.s",     0, INSN_CLASS_ZFINX,   "d,s,t,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
>  {"fdiv.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
>  {"fdiv.s",     0, INSN_CLASS_F,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
> +{"fdiv.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
> +{"fdiv.s",     0, INSN_CLASS_ZFINX,   "d,s,t,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
>  {"fsqrt.s",    0, INSN_CLASS_F,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
>  {"fsqrt.s",    0, INSN_CLASS_F,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
> +{"fsqrt.s",    0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
> +{"fsqrt.s",    0, INSN_CLASS_ZFINX,   "d,s,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
>  {"fmin.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
> +{"fmin.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
>  {"fmax.s",     0, INSN_CLASS_F,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
> +{"fmax.s",     0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
>  {"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
>  {"fmadd.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
> +{"fmadd.s",    0, INSN_CLASS_ZFINX,   "d,s,t,r",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
> +{"fmadd.s",    0, INSN_CLASS_ZFINX,   "d,s,t,r,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
>  {"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
>  {"fnmadd.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
> +{"fnmadd.s",   0, INSN_CLASS_ZFINX,   "d,s,t,r",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
> +{"fnmadd.s",   0, INSN_CLASS_ZFINX,   "d,s,t,r,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
>  {"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
>  {"fmsub.s",    0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
> +{"fmsub.s",    0, INSN_CLASS_ZFINX,   "d,s,t,r",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fmsub.s",    0, INSN_CLASS_ZFINX,   "d,s,t,r,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
>  {"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
>  {"fnmsub.s",   0, INSN_CLASS_F,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
> +{"fnmsub.s",   0, INSN_CLASS_ZFINX,   "d,s,t,r",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fnmsub.s",   0, INSN_CLASS_ZFINX,   "d,s,t,r,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
>  {"fcvt.w.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
>  {"fcvt.w.s",   0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
> +{"fcvt.w.s",   0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.s",   0, INSN_CLASS_ZFINX,   "d,s,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
>  {"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
>  {"fcvt.wu.s",  0, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
> +{"fcvt.wu.s",  0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.s",  0, INSN_CLASS_ZFINX,   "d,s,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
>  {"fcvt.s.w",   0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.w",   0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
> +{"fcvt.s.w",   0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.w",   0, INSN_CLASS_ZFINX,   "d,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
>  {"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.wu",  0, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
> +{"fcvt.s.wu",  0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.wu",  0, INSN_CLASS_ZFINX,   "d,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
>  {"fclass.s",   0, INSN_CLASS_F,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
> +{"fclass.s",   0, INSN_CLASS_ZFINX,   "d,s",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
>  {"feq.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
> +{"feq.s",      0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
>  {"flt.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"flt.s",      0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
>  {"fle.s",      0, INSN_CLASS_F,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fle.s",      0, INSN_CLASS_ZFINX,   "d,s,t",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
>  {"fgt.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"fgt.s",      0, INSN_CLASS_ZFINX,   "d,t,s",    MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
>  {"fge.s",      0, INSN_CLASS_F,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fge.s",      0, INSN_CLASS_ZFINX,   "d,t,s",    MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
>  {"fcvt.l.s",  64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
>  {"fcvt.l.s",  64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
> +{"fcvt.l.s",  64, INSN_CLASS_ZFINX, "d,s",  MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
> +{"fcvt.l.s",  64, INSN_CLASS_ZFINX, "d,s,m",  MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
>  {"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
>  {"fcvt.lu.s", 64, INSN_CLASS_F,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s",  MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s,m",  MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
>  {"fcvt.s.l",  64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.l",  64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
> +{"fcvt.s.l",  64, INSN_CLASS_ZFINX, "d,s",  MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.l",  64, INSN_CLASS_ZFINX, "d,s,m",  MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
>  {"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.lu", 64, INSN_CLASS_F,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s",  MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s,m",  MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
>
>  /* Double-precision floating-point instruction subset.  */
>  {"fld",        0, INSN_CLASS_D_AND_C, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
> @@ -592,55 +639,103 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fsd",        0, INSN_CLASS_D,   "T,A,s",     0, (int) M_FSD, match_never, INSN_MACRO },
>  {"fmv.d",      0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fneg.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.d",     0, INSN_CLASS_ZDINX,   "d,x",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fabs.d",     0, INSN_CLASS_D,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.d",     0, INSN_CLASS_ZDINX,   "d,x",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fsgnj.d",    0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
> +{"fsgnj.d",    0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
>  {"fsgnjn.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
> +{"fsgnjn.d",   0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
>  {"fsgnjx.d",   0, INSN_CLASS_D,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
> +{"fsgnjx.d",   0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
>  {"fadd.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
>  {"fadd.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
> +{"fadd.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
> +{"fadd.d",     0, INSN_CLASS_ZDINX,   "d,s,t,m",  MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
>  {"fsub.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
>  {"fsub.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
> +{"fsub.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
> +{"fsub.d",     0, INSN_CLASS_ZDINX,   "d,s,t,m",  MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
>  {"fmul.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
>  {"fmul.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
> +{"fmul.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
> +{"fmul.d",     0, INSN_CLASS_ZDINX,   "d,s,t,m",  MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
>  {"fdiv.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
>  {"fdiv.d",     0, INSN_CLASS_D,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
> +{"fdiv.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
> +{"fdiv.d",     0, INSN_CLASS_ZDINX,   "d,s,t,m",  MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
>  {"fsqrt.d",    0, INSN_CLASS_D,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
>  {"fsqrt.d",    0, INSN_CLASS_D,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
> +{"fsqrt.d",    0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
> +{"fsqrt.d",    0, INSN_CLASS_ZDINX,   "d,s,m",  MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
>  {"fmin.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
> +{"fmin.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
>  {"fmax.d",     0, INSN_CLASS_D,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
> +{"fmax.d",     0, INSN_CLASS_ZDINX,   "d,s,t",  MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
>  {"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
>  {"fmadd.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
> +{"fmadd.d",    0, INSN_CLASS_ZDINX,   "d,s,t,r",  MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
> +{"fmadd.d",    0, INSN_CLASS_ZDINX,   "d,s,t,r,m",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
>  {"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
>  {"fnmadd.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
> +{"fnmadd.d",   0, INSN_CLASS_ZDINX,   "d,s,t,r",  MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
> +{"fnmadd.d",   0, INSN_CLASS_ZDINX,   "d,s,t,r,m",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
>  {"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
>  {"fmsub.d",    0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
> +{"fmsub.d",    0, INSN_CLASS_ZDINX,   "d,s,t,r",  MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
> +{"fmsub.d",    0, INSN_CLASS_ZDINX,   "d,s,t,r,m",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
>  {"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
>  {"fnmsub.d",   0, INSN_CLASS_D,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
> +{"fnmsub.d",   0, INSN_CLASS_ZDINX,   "d,s,t,r",  MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
> +{"fnmsub.d",   0, INSN_CLASS_ZDINX,   "d,s,t,r,m",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
>  {"fcvt.w.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.w.d",   0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
> +{"fcvt.w.d",   0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.w.d",   0, INSN_CLASS_ZDINX,   "d,s,m",  MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
>  {"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.wu.d",  0, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
> +{"fcvt.wu.d",  0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.d",  0, INSN_CLASS_ZDINX,   "d,s,m",  MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
>  {"fcvt.d.w",   0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.w",   0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
>  {"fcvt.d.wu",  0, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.wu",  0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
>  {"fcvt.d.s",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.s",   0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
>  {"fcvt.s.d",   0, INSN_CLASS_D,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.d",   0, INSN_CLASS_D,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
> +{"fcvt.s.d",   0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.d",   0, INSN_CLASS_ZDINX,   "d,s,m",  MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
>  {"fclass.d",   0, INSN_CLASS_D,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
> +{"fclass.d",   0, INSN_CLASS_ZDINX,   "d,s",  MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
>  {"feq.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
> +{"feq.d",      0, INSN_CLASS_ZDINX,   "d,s,t",    MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
>  {"flt.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"flt.d",      0, INSN_CLASS_ZDINX,   "d,s,t",    MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
>  {"fle.d",      0, INSN_CLASS_D,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fle.d",      0, INSN_CLASS_ZDINX,   "d,s,t",    MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
>  {"fgt.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"fgt.d",      0, INSN_CLASS_ZDINX,   "d,t,s",    MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
>  {"fge.d",      0, INSN_CLASS_D,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fge.d",      0, INSN_CLASS_ZDINX,   "d,t,s",    MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
>  {"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
>  {"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
>  {"fcvt.l.d",  64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.l.d",  64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
> +{"fcvt.l.d",  64, INSN_CLASS_ZDINX, "d,s",  MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.l.d",  64, INSN_CLASS_ZDINX, "d,s,m",  MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
>  {"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.lu.d", 64, INSN_CLASS_D,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s",  MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s,m",  MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
>  {"fcvt.d.l",  64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.d.l",  64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
> +{"fcvt.d.l",  64, INSN_CLASS_ZDINX, "d,s",  MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.d.l",  64, INSN_CLASS_ZDINX, "d,s,m",  MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
>  {"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.d.lu", 64, INSN_CLASS_D,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s",  MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s,m",  MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
>
>  /* Quad-precision floating-point instruction subset.  */
>  {"flq",        0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
> @@ -649,58 +744,109 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_FSQ, match_never, INSN_MACRO },
>  {"fmv.q",      0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fneg.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.q",     0, INSN_CLASS_ZQINX,   "d,x",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fabs.q",     0, INSN_CLASS_Q,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.q",     0, INSN_CLASS_ZQINX,   "d,x",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
>  {"fsgnj.q",    0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> +{"fsgnj.q",    0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
>  {"fsgnjn.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> +{"fsgnjn.q",   0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
>  {"fsgnjx.q",   0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> +{"fsgnjx.q",   0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
>  {"fadd.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
>  {"fadd.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> +{"fadd.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
> +{"fadd.q",     0, INSN_CLASS_ZQINX,   "d,s,t,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
>  {"fsub.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
>  {"fsub.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> +{"fsub.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fsub.q",     0, INSN_CLASS_ZQINX,   "d,s,t,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
>  {"fmul.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
>  {"fmul.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> +{"fmul.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
> +{"fmul.q",     0, INSN_CLASS_ZQINX,   "d,s,t,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
>  {"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
>  {"fdiv.q",     0, INSN_CLASS_Q,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> +{"fdiv.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
> +{"fdiv.q",     0, INSN_CLASS_ZQINX,   "d,s,t,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
>  {"fsqrt.q",    0, INSN_CLASS_Q,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
>  {"fsqrt.q",    0, INSN_CLASS_Q,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> +{"fsqrt.q",    0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
> +{"fsqrt.q",    0, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
>  {"fmin.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> +{"fmin.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
>  {"fmax.q",     0, INSN_CLASS_Q,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> +{"fmax.q",     0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
>  {"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
>  {"fmadd.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> +{"fmadd.q",    0, INSN_CLASS_ZQINX,   "d,s,t,r",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fmadd.q",    0, INSN_CLASS_ZQINX,   "d,s,t,r,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
>  {"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
>  {"fnmadd.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> +{"fnmadd.q",   0, INSN_CLASS_ZQINX,   "d,s,t,r",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fnmadd.q",   0, INSN_CLASS_ZQINX,   "d,s,t,r,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
>  {"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
>  {"fmsub.q",    0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> +{"fmsub.q",    0, INSN_CLASS_ZQINX,   "d,s,t,r",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fmsub.q",    0, INSN_CLASS_ZQINX,   "d,s,t,r,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
>  {"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
>  {"fnmsub.q",   0, INSN_CLASS_Q,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> +{"fnmsub.q",   0, INSN_CLASS_ZQINX,   "d,s,t,r",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fnmsub.q",   0, INSN_CLASS_ZQINX,   "d,s,t,r,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
>  {"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.w.q",   0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> +{"fcvt.w.q",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.q",   0, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
>  {"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.wu.q",  0, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> +{"fcvt.wu.q",  0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.q",  0, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
>  {"fcvt.q.w",   0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.w",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
>  {"fcvt.q.wu",  0, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.wu",  0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
>  {"fcvt.q.s",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.s",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
>  {"fcvt.q.d",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.d",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.s.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> +{"fcvt.s.q",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.q",   0, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
>  {"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.d.q",   0, INSN_CLASS_Q,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> +{"fcvt.d.q",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.q",   0, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
>  {"fclass.q",   0, INSN_CLASS_Q,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> +{"fclass.q",   0, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
>  {"feq.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> +{"feq.q",      0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
>  {"flt.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"flt.q",      0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
>  {"fle.q",      0, INSN_CLASS_Q,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fle.q",      0, INSN_CLASS_ZQINX,   "d,s,t",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
>  {"fgt.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"fgt.q",      0, INSN_CLASS_ZQINX,   "d,t,s",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
>  {"fge.q",      0, INSN_CLASS_Q,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fge.q",      0, INSN_CLASS_ZQINX,   "d,t,s",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
>  {"fmv.x.q",   64, INSN_CLASS_Q,   "d,S",       MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
>  {"fmv.q.x",   64, INSN_CLASS_Q,   "D,s",       MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
>  {"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.l.q",  64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> +{"fcvt.l.q",  64, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.l.q",  64, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
>  {"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.lu.q", 64, INSN_CLASS_Q,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
>  {"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.q.l",  64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
> +{"fcvt.q.l",  64, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.l",  64, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
>  {"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
>  {"fcvt.q.lu", 64, INSN_CLASS_Q,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX,   "d,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX,   "d,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
>
>  /* Compressed instructions.  */
>  {"c.unimp",    0, INSN_CLASS_C,   "",          0, 0xffffU,  match_opcode, 0 },
> --
> 2.25.1
>
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