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[RFC PATCH 3/6] RISC-V: Add Zvkh[a,b] ISA extension support

Jeff Law jeffreyalaw@gmail.com
Wed Dec 21 21:24:15 GMT 2022 
On 12/21/22 10:07, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> This commit adds the Zvkh[a,b] ISA extension instructions, which are part
> of the vector crypto extensions.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>   bfd/elfxx-riscv.c                     | 13 +++++++++++++
>   gas/testsuite/gas/riscv/zvkha.d       | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvkha_zvkhb.s |  3 +++
>   gas/testsuite/gas/riscv/zvkhb.d       | 12 ++++++++++++
>   include/opcode/riscv-opc.h            | 11 +++++++++++
>   include/opcode/riscv.h                |  3 +++
>   opcodes/riscv-opc.c                   |  5 +++++
>   7 files changed, 59 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkha.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
>   create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
Looks reasonable to me.  Just one comment nit below...



> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index bb716c8c9d0..35d3e653147 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1834,6 +1834,11 @@ const struct riscv_opcode riscv_opcodes[] =
>   /* Zvkg instructions.  */
>   {"vghmac.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0},
>   
> +/* Xvkh[a,b] instructions.  */
Are these X or Z?

Jeff
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