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[PATCH 2/2] libopcodes/aarch64: add support for disassembler styling

Nick Clifton nickc@redhat.com
Wed Jun 22 11:15:36 GMT 2022 
Hi Andrew,

> I do still have a few questions about how some elements should be
> styled, consider this instruction:
> 
>      add     x1, x2, x3, lsr #1
>         ~~~~~  ~~  ~~  ~~   ~      Plain text.
>      ~~~                           Mnemonic.
>              ~~  ~~  ~~            Register.
> 	                    ~~    Immediate.
>                          ???       What to use here?
> 
> The current patch formats the 'lsr' as text, but I wonder if this
> would be better formatted as mnemonic?  Or maybe it should be
> considered part of the immediate? 

My $0.02 worth: It is not an immediate - in fact that instruction does
not have any immediates in it - nor is it just plain text.  I suppose
that you might consider it as being an extension of the mnemonic, but
that also feels wrong to me.  Could you create a new class for this
part of the instruction ?  eg 'shifter' or 'sub-mnemonic'.  If not then
I would go with mnemonic as that is the closest approximation.  IMHO...


> I have a similar question for how to format 'ge' in:
> 
>      ccmp    x1, x2, #0xa, ge

The same reasoning applies here I feel.  This is "ccmp-ge" instruction
with the condition expressed as a separate field in the disassembled
text.  Ideally a "condition-code" class could be used to express its
style, but if that is not possible then mnemonic is the next best thing.


> And how to format 'sxtb' in:
>  >      adds    x0, sp, w0, sxtb

Ditto.  Maybe an "extender" class could be used here ?


The patch itself looks good to me, but I would like to wait to see if
anyone else has any comments on the code before approving it.

Cheers
   Nick
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