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[PATCH 01/10] Support Intel AVX-IFMA

H.J. Lu hjl.tools@gmail.com
Mon Oct 17 22:23:32 GMT 2022 
On Sat, Oct 15, 2022 at 11:39 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.10.2022 20:10, H.J. Lu wrote:
> > On Fri, Oct 14, 2022 at 2:52 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>> From: wwwhhhyyy <hongyu.wang@intel.com>
> >>>
> >>> x86: Support Intel AVX-IFMA
> >>>
> >>> Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
> >>> cleared by default.  Without {vex} pseudo prefix, Intel IFMA instructions
> >>> are encoded with EVEX prefix.  {vex} pseudo prefix will turn on VEX
> >>> encoding for Intel IFMA instructions.
> >>
> >> I firmly object to the proliferation of this mis-feature. As expressed
> >> before for AVX-VNNI, as long as the user has disabled AVX512 (or
> >> respective sub-features thereof), there should be no need to use {vex} in
> >> the source code. There's also no reason at all to make the disassembler
> >> print {vex} prefixes - we don't do so for any other insns (apart from
> >> AVX-VNNI) where an ambiguity exists between their VEX and EVEX encodings
> >> (when none of the EVEX-specific features is used).
> >
> > The {vex} prefix is used with AVX-IFMA instructions so that IFMA instructions
> > without a prefix, which are generated by compilers or handwritten, will be
> > always encoded with EVEX.
>
> So again: Why is this necessary when a programmer disabled AVX512? I fully
> agree we need to pick the EVEX encoding by default if available, but I see
> no reason whatsoever to insist on a {vex} prefix when the EVEX variant is
> unavailable anyway. As you said back at the time for AVX-VNNI - this was a
> design decision taken at Intel. Which is fine for a draft implementation.
> But decisions for an open source project should be taken in the open, and
> opinions of others should not simply be put off.
>

We can discuss how to initialize i.vec_encoding.  But it is orthogonal to
this patch.

-- 
H.J.
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