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[PATCH 10/10] Support Intel PREFETCHI

Cui, Lili lili.cui@intel.com
Tue Oct 25 07:49:01 GMT 2022 
> On 19.10.2022 17:15, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> >    SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> >    SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> >    SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> > +  SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> >  };
> >
> >  #undef SUBARCH
> > @@ -4522,7 +4523,8 @@ load_insn_p (void)
> >      {
> >        /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> >  	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> > -	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
> > +	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> > +	 prefetchit1.  */
> >        if (i.tm.opcode_modifier.anysize)
> >  	return 0;
> >
> 
> There's still no change in this file making sure that the new insns are _only_
> accepted with RIP-relative addressing. See my earlier comments.
> 
Hi Jan,
I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.

Lili.
> Jan
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