[PATCH v2] RISC-V: Add support for ssdbltrp and smdbltrp extension.
chendongyan
chendongyan@isrc.iscas.ac.cn
Fri Nov 29 07:09:58 GMT 2024
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Thanks for your review, merge the two additions and remove the changes of csr support in the next version. From d88e7f2231ea5c138f2e63c25b96721b8e46e47f Mon Sep 17 00:00:00 2001 From: Dongyan Chen <chendongyan@isrc.iscas.ac.cn> Date: Wed, 27 Nov 2024 17:56:39 +0800 Subject: [PATCH v3] RISC-V: Add support for ssdbltrp and smdbltrp extension. This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc [2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc Changes for v2: - Move the additions in the "gas/News" section to the top of the file. - Modify the indentation format of the case in the "gas/config/tc-riscv.c" file. Changes for v3: - Merge the two additions in the "gas/NEWS" into one. - Remove the changes in the "config/tc-riscv.c". bfd/ChangeLog: * elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. --- bfd/elfxx-riscv.c | 4 ++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 2 ++ 3 files changed, 8 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 45da83e6926..49b4d5ca4eb 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1272,6 +1272,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sstvala", "+zicsr", check_implicit_always}, {"sstvecd", "+zicsr", check_implicit_always}, {"ssu64xl", "+zicsr", check_implicit_always}, + {"ssdbltrp", "+zicsr", check_implicit_always}, + {"smdbltrp", "+zicsr", check_implicit_always}, {"svade", "+zicsr", check_implicit_always}, {"svadu", "+zicsr", check_implicit_always}, @@ -1458,6 +1460,8 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index 23eda334ec6..e8fa3f4a16e 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -13,6 +13,8 @@ (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf). + Add support for the RISC-V s[sm]dbltrp extension, version 1.0. + Changes in 2.43: * Add support for LoongArch .option for fine-grained control of assembly diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 71cccb77102..c3e51c0ca2b 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -127,6 +127,8 @@ All available -march extensions for RISC-V: sstvala 1.0 sstvecd 1.0 ssu64xl 1.0 + ssdbltrp 1.0 + smdbltrp 1.0 svade 1.0 svadu 1.0 svbare 1.0 -- 2.43.0 -----原始邮件----- 发件人:"Nelson Chu" <nelson@rivosinc.com> 发送时间:2024-11-29 10:08:30 (星期五) 收件人: "Dongyan Chen" <chendongyan@isrc.iscas.ac.cn> 抄送: binutils@sourceware.org, kito.cheng@gmail.com, jbeulich@suse.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.ac.cn 主题: Re: [PATCH v2] RISC-V: Add support for ssdbltrp and smdbltrp extension. On Thu, Nov 28, 2024 at 8:35 PM Dongyan Chen <chendongyan@isrc.iscas.ac.cn> wrote: This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc [2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc Changes for v2: - Move the additions in the "gas/News" section to the top of the file. - Modify the indentation format of the case in the "gas/config/tc-riscv.c" file. bfd/ChangeLog: * elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (enum riscv_csr_class): (riscv_csr_address): Add CSR classes for Ssdbltrp/Smdbltrp. * testsuite/gas/riscv/march-help.l: Updated. --- bfd/elfxx-riscv.c | 4 ++++ gas/NEWS | 4 ++++ gas/config/tc-riscv.c | 8 ++++++++ gas/testsuite/gas/riscv/march-help.l | 2 ++ 4 files changed, 18 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 45da83e6926..49b4d5ca4eb 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1272,6 +1272,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sstvala", "+zicsr", check_implicit_always}, {"sstvecd", "+zicsr", check_implicit_always}, {"ssu64xl", "+zicsr", check_implicit_always}, + {"ssdbltrp", "+zicsr", check_implicit_always}, + {"smdbltrp", "+zicsr", check_implicit_always}, {"svade", "+zicsr", check_implicit_always}, {"svadu", "+zicsr", check_implicit_always}, @@ -1458,6 +1460,8 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index 23eda334ec6..a208a1fcc51 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -13,6 +13,10 @@ (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf). + Add support for the RISC-V ssdbltrp extension, version 1.0. + + Add support for the RISC-V smdbltrp extension, version 1.0. + Can we merge these two line into the above one? Changes in 2.43: * Add support for LoongArch .option for fine-grained control of assembly diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 3fb7727c250..ea865939b70 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -102,6 +102,8 @@ enum riscv_csr_class CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ CSR_CLASS_SSTC_32, /* Sstc RV32 only */ CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ + CSR_CLASS_SSDBLTRP, /* Ssdbltrp only */ + CSR_CLASS_SMDBLTRP, /* Smdbltrp only */ CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */ }; @@ -1150,6 +1152,12 @@ riscv_csr_address (const char *csr_name, || csr_class == CSR_CLASS_SSTC_AND_H_32); extension = "sstc"; break; + case CSR_CLASS_SSDBLTRP: + extension = "ssdbltrp"; + break; + case CSR_CLASS_SMDBLTRP: + extension = "smdbltrp"; + break; I think we don't need these change since there seems no any new csr support in this patch. Thanks Nelson case CSR_CLASS_DEBUG: break; case CSR_CLASS_XTHEADVECTOR: diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 71cccb77102..c3e51c0ca2b 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -127,6 +127,8 @@ All available -march extensions for RISC-V: sstvala 1.0 sstvecd 1.0 ssu64xl 1.0 + ssdbltrp 1.0 + smdbltrp 1.0 svade 1.0 svadu 1.0 svbare 1.0 -- 2.43.0 -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://sourceware.org/pipermail/binutils/attachments/20241129/9f06cd96/attachment-0001.htm>
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