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[PATCH v6] AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.

Alice Carlotti alice.carlotti@arm.com
Mon Dec 22 16:14:05 GMT 2025 
On Mon, Dec 22, 2025 at 08:55:57AM +0100, Jan Beulich wrote:
> On 17.12.2025 13:31, Sivan Shani wrote:
> > --- /dev/null
> > +++ b/gas/testsuite/gas/aarch64/sme2p3.d
> > @@ -0,0 +1,33 @@
> > +#as: -march=armv8-a+sme2p3
> > +#objdump: -dr
> > +
> > +.*:     file format .*
> > +
> > +Disassembly of section \.text:
> > +
> > +0+ <\.text>:
> > + *[0-9a-f]+:	c08a0000 	luti6	{z0.b-z3.b}, zt0, {z0-z2}
> > + *[0-9a-f]+:	c08a001c 	luti6	{z28.b-z31.b}, zt0, {z0-z2}
> > + *[0-9a-f]+:	c08a0380 	luti6	{z0.b-z3.b}, zt0, {z7-z9}
> > + *[0-9a-f]+:	c09a0000 	luti6	{z0.b, z4.b, z8.b, z12.b}, zt0, {z0-z2}
> > + *[0-9a-f]+:	c09a0013 	luti6	{z19.b, z23.b, z27.b, z31.b}, zt0, {z0-z2}
> > + *[0-9a-f]+:	c09a0380 	luti6	{z0.b, z4.b, z8.b, z12.b}, zt0, {z7-z9}
> > + *[0-9a-f]+:	c0c84000 	luti6	z0.b, zt0, z0
> > + *[0-9a-f]+:	c0c8401f 	luti6	z31.b, zt0, z0
> > + *[0-9a-f]+:	c0c843e0 	luti6	z0.b, zt0, z31
> > +
> > + *[0-9a-f]+:	c120f400 	luti6	{z0.h-z3.h}, {z0.h-z1.h}, {z0-z1}\[0\]
> 
> For the middle operand the spec says to use comma, not dash as list separator.
> While this may be intentionally different in binutils, ...
> 
> > + *[0-9a-f]+:	c120f41c 	luti6	{z28.h-z31.h}, {z0.h-z1.h}, {z0-z1}\[0\]
> > + *[0-9a-f]+:	c120f7c0 	luti6	{z0.h-z3.h}, {z30.h-z31.h}, {z0-z1}\[0\]
> > + *[0-9a-f]+:	c120f7e0 	luti6	{z0.h-z3.h}, {z31.h-z0.h}, {z0-z1}\[0\]
> 
> ... the latest here I question this being a reasonable representation.
> 
...
> Jan

The spec permits both hyphenated and comma-separated syntax for register lists,
but it's a bit vague or inconsistent about the preferred disassembly.

The Arm ARM (M.a) says:

C1.2.6.5.1 - SIMD vector register list
Where an instruction operates on multiple SIMD&FP or SVE registers, for example
vector load/store structure and table lookup operations, the registers are
specified as a list enclosed by curly braces. This list consists of either a
sequence of registers separated by commas, or a register range separated by a
hyphen. The registers must be numbered in increasing order, modulo 32, in
increments of one. The hyphenated form is preferred for disassembly if there
are more than two registers in the list and the register numbers are increasing
by 1. The following examples are equivalent representations of a set of four
registers V4 to V7, each holding four lanes of 32-bit elements:


The (retired) SME supplement (DDI0616 B.a) said:

The preferred disassembly for a Z multi-vector operand of consecutively
numbered Z vectors is a dash-separated register range, for example { Z0.S-Z1.S }
or { Z30.B-Z1.B }. Toolchains must also support assembler source code that
uses the alternative comma-separated list notation, for example { Z0.S, Z1.S }
or { Z30.B, Z31.B, Z0.B, Z1.B }. Disassemblers can provide an option to select
between the dash-separated range and comma-separated list notations.


(Strided vector register lists are mentioned separately in the SME supplement,
but are overlooked in that section of the Arm ARM.)


We currently follow the declaration in the SME supplement for all vector
register lists.  This is also consistent with a pedantic reading of the Arm
ARM, because that doesn't state that the comma-separated form is explicitly
preferred in any case.

Alice
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