[PATCH v5 2/4] aarch64: Add support for POE2 system registers
Srinath Parvathaneni
srinath.parvathaneni@arm.com
Tue Dec 23 18:51:02 GMT 2025
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Tue Dec 23 18:51:02 GMT 2025
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This patch adds support for POE2 system registers which are available by default, however if guarding restrictions are enabled using -menable-sysreg-checking than "+poe2" option need to specified to the -march. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com> --- .../gas/aarch64/sysreg/poe2-sysreg-1.d | 537 +++++++++++++++++ .../gas/aarch64/sysreg/poe2-sysreg-1.s | 88 +++ .../gas/aarch64/sysreg/poe2-sysreg-2.d | 538 ++++++++++++++++++ opcodes/aarch64-sys-regs.def | 264 +++++++++ 4 files changed, 1427 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s create mode 100644 gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d new file mode 100644 index 00000000000..9ddaf2d4d91 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.d @@ -0,0 +1,537 @@ +#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv8-a+poe2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51820c0 msr dpotbr0_el1, x0 +.*: d53820c0 mrs x0, dpotbr0_el1 +.*: d51820e0 msr dpotbr1_el1, x0 +.*: d53820e0 mrs x0, dpotbr1_el1 +.*: d51d20c0 msr dpotbr0_el12, x0 +.*: d53d20c0 mrs x0, dpotbr0_el12 +.*: d51d20e0 msr dpotbr1_el12, x0 +.*: d53d20e0 mrs x0, dpotbr1_el12 +.*: d51c20c0 msr dpotbr0_el2, x0 +.*: d53c20c0 mrs x0, dpotbr0_el2 +.*: d51c20e0 msr dpotbr1_el2, x0 +.*: d53c20e0 mrs x0, dpotbr1_el2 +.*: d51e20c0 msr dpotbr0_el3, x0 +.*: d53e20c0 mrs x0, dpotbr0_el3 +.*: d51bd000 msr tpidr3_el0, x0 +.*: d53bd000 mrs x0, tpidr3_el0 +.*: d518d000 msr tpidr3_el1, x0 +.*: d538d000 mrs x0, tpidr3_el1 +.*: d51dd000 msr tpidr3_el12, x0 +.*: d53dd000 mrs x0, tpidr3_el12 +.*: d51cd000 msr tpidr3_el2, x0 +.*: d53cd000 mrs x0, tpidr3_el2 +.*: d51ed000 msr tpidr3_el3, x0 +.*: d53ed000 mrs x0, tpidr3_el3 +.*: d5182080 msr irtbru_el1, x0 +.*: d5382080 mrs x0, irtbru_el1 +.*: d51d2080 msr irtbru_el12, x0 +.*: d53d2080 mrs x0, irtbru_el12 +.*: d51c2080 msr irtbru_el2, x0 +.*: d53c2080 mrs x0, irtbru_el2 +.*: d51820a0 msr irtbrp_el1, x0 +.*: d53820a0 mrs x0, irtbrp_el1 +.*: d51d20a0 msr irtbrp_el12, x0 +.*: d53d20a0 mrs x0, irtbrp_el12 +.*: d51c20a0 msr irtbrp_el2, x0 +.*: d53c20a0 mrs x0, irtbrp_el2 +.*: d51e20a0 msr irtbrp_el3, x0 +.*: d53e20a0 mrs x0, irtbrp_el3 +.*: d51821e0 msr ldstt_el1, x0 +.*: d53821e0 mrs x0, ldstt_el1 +.*: d51d21e0 msr ldstt_el12, x0 +.*: d53d21e0 mrs x0, ldstt_el12 +.*: d51c21e0 msr ldstt_el2, x0 +.*: d53c21e0 mrs x0, ldstt_el2 +.*: d5184040 msr stindex_el1, x0 +.*: d5384040 mrs x0, stindex_el1 +.*: d51d4040 msr stindex_el12, x0 +.*: d53d4040 mrs x0, stindex_el12 +.*: d51c4040 msr stindex_el2, x0 +.*: d53c4040 mrs x0, stindex_el2 +.*: d51e4040 msr stindex_el3, x0 +.*: d53e4040 mrs x0, stindex_el3 +.*: d51b4060 msr tindex_el0, x0 +.*: d53b4060 mrs x0, tindex_el0 +.*: d5184060 msr tindex_el1, x0 +.*: d5384060 mrs x0, tindex_el1 +.*: d51d4060 msr tindex_el12, x0 +.*: d53d4060 mrs x0, tindex_el12 +.*: d51c4060 msr tindex_el2, x0 +.*: d53c4060 mrs x0, tindex_el2 +.*: d51e4060 msr tindex_el3, x0 +.*: d53e4060 mrs x0, tindex_el3 +.*: d518a2c0 msr tttbru_el1, x0 +.*: d538a2c0 mrs x0, tttbru_el1 +.*: d51da2c0 msr tttbru_el12, x0 +.*: d53da2c0 mrs x0, tttbru_el12 +.*: d51ca2c0 msr tttbru_el2, x0 +.*: d53ca2c0 mrs x0, tttbru_el2 +.*: d518a2e0 msr tttbrp_el1, x0 +.*: d538a2e0 mrs x0, tttbrp_el1 +.*: d51da2e0 msr tttbrp_el12, x0 +.*: d53da2e0 mrs x0, tttbrp_el12 +.*: d51ca2e0 msr tttbrp_el2, x0 +.*: d53ca2e0 mrs x0, tttbrp_el2 +.*: d51ea2e0 msr tttbrp_el3, x0 +.*: d53ea2e0 mrs x0, tttbrp_el3 +.*: d51b4540 msr dpocr_el0, x0 +.*: d53b4540 mrs x0, dpocr_el0 +.*: d51c2220 msr vnccr_el2, x0 +.*: d53c2220 mrs x0, vnccr_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s new file mode 100644 index 00000000000..4d1980b9803 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-1.s @@ -0,0 +1,88 @@ +.include "sysreg-test-utils.inc" + +.text + +.altmacro + +.macro rw_sys_reg_16 base, suffix + .rept 16 + rw_sys_reg \base\+\suffix + .endr +.endm + +// AFGDTpn_ELx system registers + rw_sys_reg_16 AFGDTP, _EL1 + rw_sys_reg_16 AFGDTP, _EL12 + rw_sys_reg_16 AFGDTP, _EL2 + rw_sys_reg_16 AFGDTP, _EL3 + rw_sys_reg_16 AFGDTU, _EL1 + rw_sys_reg_16 AFGDTU, _EL12 + rw_sys_reg_16 AFGDTU, _EL2 + +// FGDTpn_ELx system registers + rw_sys_reg_16 FGDTP, _EL1 + rw_sys_reg_16 FGDTP, _EL12 + rw_sys_reg_16 FGDTP, _EL2 + rw_sys_reg_16 FGDTP, _EL3 + rw_sys_reg_16 FGDTU, _EL1 + rw_sys_reg_16 FGDTU, _EL12 + rw_sys_reg_16 FGDTU, _EL2 + +// DPOTBRn_ELx system registers + rw_sys_reg DPOTBR0_EL1 + rw_sys_reg DPOTBR1_EL1 + rw_sys_reg DPOTBR0_EL12 + rw_sys_reg DPOTBR1_EL12 + rw_sys_reg DPOTBR0_EL2 + rw_sys_reg DPOTBR1_EL2 + rw_sys_reg DPOTBR0_EL3 + +// TPIDR3_ELx system registers + rw_sys_reg TPIDR3_EL0 + rw_sys_reg TPIDR3_EL1 + rw_sys_reg TPIDR3_EL12 + rw_sys_reg TPIDR3_EL2 + rw_sys_reg TPIDR3_EL3 + +// IRTBRp_ELx system registers + rw_sys_reg IRTBRU_EL1 + rw_sys_reg IRTBRU_EL12 + rw_sys_reg IRTBRU_EL2 + rw_sys_reg IRTBRP_EL1 + rw_sys_reg IRTBRP_EL12 + rw_sys_reg IRTBRP_EL2 + rw_sys_reg IRTBRP_EL3 + +// LDSTT_ELx system registers + rw_sys_reg LDSTT_EL1 + rw_sys_reg LDSTT_EL12 + rw_sys_reg LDSTT_EL2 + +// STINDEX_ELx system registers + rw_sys_reg STINDEX_EL1 + rw_sys_reg STINDEX_EL12 + rw_sys_reg STINDEX_EL2 + rw_sys_reg STINDEX_EL3 + +// TINDEX_ELx system registers + rw_sys_reg TINDEX_EL0 + rw_sys_reg TINDEX_EL1 + rw_sys_reg TINDEX_EL12 + rw_sys_reg TINDEX_EL2 + rw_sys_reg TINDEX_EL3 + +// TTTBRp_ELx system registers + rw_sys_reg TTTBRU_EL1 + rw_sys_reg TTTBRU_EL12 + rw_sys_reg TTTBRU_EL2 + rw_sys_reg TTTBRP_EL1 + rw_sys_reg TTTBRP_EL12 + rw_sys_reg TTTBRP_EL2 + rw_sys_reg TTTBRP_EL3 + +// DPOCR_EL0 system registers + rw_sys_reg DPOCR_EL0 + +// VNCCR_EL2 system registers + rw_sys_reg VNCCR_EL2 +.noaltmacro diff --git a/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d new file mode 100644 index 00000000000..e704f385d69 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/poe2-sysreg-2.d @@ -0,0 +1,538 @@ +#as: -I$srcdir/$subdir -march=armv8-a +#source: poe2-sysreg-1.s +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d5183600 msr afgdtp0_el1, x0 +.*: d5383600 mrs x0, afgdtp0_el1 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51d3620 msr afgdtp1_el12, x0 +.*: d53d3620 mrs x0, afgdtp1_el12 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51c3640 msr afgdtp2_el2, x0 +.*: d53c3640 mrs x0, afgdtp2_el2 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d51e3660 msr afgdtp3_el3, x0 +.*: d53e3660 mrs x0, afgdtp3_el3 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d5183880 msr afgdtu4_el1, x0 +.*: d5383880 mrs x0, afgdtu4_el1 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51d38a0 msr afgdtu5_el12, x0 +.*: d53d38a0 mrs x0, afgdtu5_el12 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51c38c0 msr afgdtu6_el2, x0 +.*: d53c38c0 mrs x0, afgdtu6_el2 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51832e0 msr fgdtp7_el1, x0 +.*: d53832e0 mrs x0, fgdtp7_el1 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51d3300 msr fgdtp8_el12, x0 +.*: d53d3300 mrs x0, fgdtp8_el12 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51c3320 msr fgdtp9_el2, x0 +.*: d53c3320 mrs x0, fgdtp9_el2 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d51e3340 msr fgdtp10_el3, x0 +.*: d53e3340 mrs x0, fgdtp10_el3 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d5183560 msr fgdtu11_el1, x0 +.*: d5383560 mrs x0, fgdtu11_el1 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51d3580 msr fgdtu12_el12, x0 +.*: d53d3580 mrs x0, fgdtu12_el12 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51c35a0 msr fgdtu13_el2, x0 +.*: d53c35a0 mrs x0, fgdtu13_el2 +.*: d51820c0 msr dpotbr0_el1, x0 +.*: d53820c0 mrs x0, dpotbr0_el1 +.*: d51820e0 msr dpotbr1_el1, x0 +.*: d53820e0 mrs x0, dpotbr1_el1 +.*: d51d20c0 msr dpotbr0_el12, x0 +.*: d53d20c0 mrs x0, dpotbr0_el12 +.*: d51d20e0 msr dpotbr1_el12, x0 +.*: d53d20e0 mrs x0, dpotbr1_el12 +.*: d51c20c0 msr dpotbr0_el2, x0 +.*: d53c20c0 mrs x0, dpotbr0_el2 +.*: d51c20e0 msr dpotbr1_el2, x0 +.*: d53c20e0 mrs x0, dpotbr1_el2 +.*: d51e20c0 msr dpotbr0_el3, x0 +.*: d53e20c0 mrs x0, dpotbr0_el3 +.*: d51bd000 msr tpidr3_el0, x0 +.*: d53bd000 mrs x0, tpidr3_el0 +.*: d518d000 msr tpidr3_el1, x0 +.*: d538d000 mrs x0, tpidr3_el1 +.*: d51dd000 msr tpidr3_el12, x0 +.*: d53dd000 mrs x0, tpidr3_el12 +.*: d51cd000 msr tpidr3_el2, x0 +.*: d53cd000 mrs x0, tpidr3_el2 +.*: d51ed000 msr tpidr3_el3, x0 +.*: d53ed000 mrs x0, tpidr3_el3 +.*: d5182080 msr irtbru_el1, x0 +.*: d5382080 mrs x0, irtbru_el1 +.*: d51d2080 msr irtbru_el12, x0 +.*: d53d2080 mrs x0, irtbru_el12 +.*: d51c2080 msr irtbru_el2, x0 +.*: d53c2080 mrs x0, irtbru_el2 +.*: d51820a0 msr irtbrp_el1, x0 +.*: d53820a0 mrs x0, irtbrp_el1 +.*: d51d20a0 msr irtbrp_el12, x0 +.*: d53d20a0 mrs x0, irtbrp_el12 +.*: d51c20a0 msr irtbrp_el2, x0 +.*: d53c20a0 mrs x0, irtbrp_el2 +.*: d51e20a0 msr irtbrp_el3, x0 +.*: d53e20a0 mrs x0, irtbrp_el3 +.*: d51821e0 msr ldstt_el1, x0 +.*: d53821e0 mrs x0, ldstt_el1 +.*: d51d21e0 msr ldstt_el12, x0 +.*: d53d21e0 mrs x0, ldstt_el12 +.*: d51c21e0 msr ldstt_el2, x0 +.*: d53c21e0 mrs x0, ldstt_el2 +.*: d5184040 msr stindex_el1, x0 +.*: d5384040 mrs x0, stindex_el1 +.*: d51d4040 msr stindex_el12, x0 +.*: d53d4040 mrs x0, stindex_el12 +.*: d51c4040 msr stindex_el2, x0 +.*: d53c4040 mrs x0, stindex_el2 +.*: d51e4040 msr stindex_el3, x0 +.*: d53e4040 mrs x0, stindex_el3 +.*: d51b4060 msr tindex_el0, x0 +.*: d53b4060 mrs x0, tindex_el0 +.*: d5184060 msr tindex_el1, x0 +.*: d5384060 mrs x0, tindex_el1 +.*: d51d4060 msr tindex_el12, x0 +.*: d53d4060 mrs x0, tindex_el12 +.*: d51c4060 msr tindex_el2, x0 +.*: d53c4060 mrs x0, tindex_el2 +.*: d51e4060 msr tindex_el3, x0 +.*: d53e4060 mrs x0, tindex_el3 +.*: d518a2c0 msr tttbru_el1, x0 +.*: d538a2c0 mrs x0, tttbru_el1 +.*: d51da2c0 msr tttbru_el12, x0 +.*: d53da2c0 mrs x0, tttbru_el12 +.*: d51ca2c0 msr tttbru_el2, x0 +.*: d53ca2c0 mrs x0, tttbru_el2 +.*: d518a2e0 msr tttbrp_el1, x0 +.*: d538a2e0 mrs x0, tttbrp_el1 +.*: d51da2e0 msr tttbrp_el12, x0 +.*: d53da2e0 mrs x0, tttbrp_el12 +.*: d51ca2e0 msr tttbrp_el2, x0 +.*: d53ca2e0 mrs x0, tttbrp_el2 +.*: d51ea2e0 msr tttbrp_el3, x0 +.*: d53ea2e0 mrs x0, tttbrp_el3 +.*: d51b4540 msr dpocr_el0, x0 +.*: d53b4540 mrs x0, dpocr_el0 +.*: d51c2220 msr vnccr_el2, x0 +.*: d53c2220 mrs x0, vnccr_el2 diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 17c1c9d0c01..e0bb7239e26 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -45,6 +45,118 @@ SYSREG ("actlrmask_el1", CPENC (3,0,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ SYSREG ("actlrmask_el12", CPENC (3,5,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ SYSREG ("actlrmask_el2", CPENC (3,4,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */ + SYSREG ("afgdtp0_el1", CPENC (3,0,3,6,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp0_el12", CPENC (3,5,3,6,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp0_el2", CPENC (3,4,3,6,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp0_el3", CPENC (3,6,3,6,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp10_el1", CPENC (3,0,3,7,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp10_el12", CPENC (3,5,3,7,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp10_el2", CPENC (3,4,3,7,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp10_el3", CPENC (3,6,3,7,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp11_el1", CPENC (3,0,3,7,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp11_el12", CPENC (3,5,3,7,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp11_el2", CPENC (3,4,3,7,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp11_el3", CPENC (3,6,3,7,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp12_el1", CPENC (3,0,3,7,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp12_el12", CPENC (3,5,3,7,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp12_el2", CPENC (3,4,3,7,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp12_el3", CPENC (3,6,3,7,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp13_el1", CPENC (3,0,3,7,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp13_el12", CPENC (3,5,3,7,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp13_el2", CPENC (3,4,3,7,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp13_el3", CPENC (3,6,3,7,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp14_el1", CPENC (3,0,3,7,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp14_el12", CPENC (3,5,3,7,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp14_el2", CPENC (3,4,3,7,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp14_el3", CPENC (3,6,3,7,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp15_el1", CPENC (3,0,3,7,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp15_el12", CPENC (3,5,3,7,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp15_el2", CPENC (3,4,3,7,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp15_el3", CPENC (3,6,3,7,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp1_el1", CPENC (3,0,3,6,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp1_el12", CPENC (3,5,3,6,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp1_el2", CPENC (3,4,3,6,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp1_el3", CPENC (3,6,3,6,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp2_el1", CPENC (3,0,3,6,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp2_el12", CPENC (3,5,3,6,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp2_el2", CPENC (3,4,3,6,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp2_el3", CPENC (3,6,3,6,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp3_el1", CPENC (3,0,3,6,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp3_el12", CPENC (3,5,3,6,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp3_el2", CPENC (3,4,3,6,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp3_el3", CPENC (3,6,3,6,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp4_el1", CPENC (3,0,3,6,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp4_el12", CPENC (3,5,3,6,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp4_el2", CPENC (3,4,3,6,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp4_el3", CPENC (3,6,3,6,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp5_el1", CPENC (3,0,3,6,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp5_el12", CPENC (3,5,3,6,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp5_el2", CPENC (3,4,3,6,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp5_el3", CPENC (3,6,3,6,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp6_el1", CPENC (3,0,3,6,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp6_el12", CPENC (3,5,3,6,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp6_el2", CPENC (3,4,3,6,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp6_el3", CPENC (3,6,3,6,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp7_el1", CPENC (3,0,3,6,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp7_el12", CPENC (3,5,3,6,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp7_el2", CPENC (3,4,3,6,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp7_el3", CPENC (3,6,3,6,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp8_el1", CPENC (3,0,3,7,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp8_el12", CPENC (3,5,3,7,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp8_el2", CPENC (3,4,3,7,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp8_el3", CPENC (3,6,3,7,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp9_el1", CPENC (3,0,3,7,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp9_el12", CPENC (3,5,3,7,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp9_el2", CPENC (3,4,3,7,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtp9_el3", CPENC (3,6,3,7,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu0_el1", CPENC (3,0,3,8,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu0_el12", CPENC (3,5,3,8,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu0_el2", CPENC (3,4,3,8,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu10_el1", CPENC (3,0,3,9,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu10_el12", CPENC (3,5,3,9,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu10_el2", CPENC (3,4,3,9,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu11_el1", CPENC (3,0,3,9,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu11_el12", CPENC (3,5,3,9,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu11_el2", CPENC (3,4,3,9,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu12_el1", CPENC (3,0,3,9,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu12_el12", CPENC (3,5,3,9,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu12_el2", CPENC (3,4,3,9,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu13_el1", CPENC (3,0,3,9,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu13_el12", CPENC (3,5,3,9,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu13_el2", CPENC (3,4,3,9,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu14_el1", CPENC (3,0,3,9,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu14_el12", CPENC (3,5,3,9,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu14_el2", CPENC (3,4,3,9,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu15_el1", CPENC (3,0,3,9,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu15_el12", CPENC (3,5,3,9,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu15_el2", CPENC (3,4,3,9,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu1_el1", CPENC (3,0,3,8,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu1_el12", CPENC (3,5,3,8,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu1_el2", CPENC (3,4,3,8,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu2_el1", CPENC (3,0,3,8,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu2_el12", CPENC (3,5,3,8,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu2_el2", CPENC (3,4,3,8,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu3_el1", CPENC (3,0,3,8,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu3_el12", CPENC (3,5,3,8,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu3_el2", CPENC (3,4,3,8,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu4_el1", CPENC (3,0,3,8,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu4_el12", CPENC (3,5,3,8,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu4_el2", CPENC (3,4,3,8,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu5_el1", CPENC (3,0,3,8,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu5_el12", CPENC (3,5,3,8,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu5_el2", CPENC (3,4,3,8,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu6_el1", CPENC (3,0,3,8,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu6_el12", CPENC (3,5,3,8,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu6_el2", CPENC (3,4,3,8,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu7_el1", CPENC (3,0,3,8,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu7_el12", CPENC (3,5,3,8,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu7_el2", CPENC (3,4,3,8,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu8_el1", CPENC (3,0,3,9,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu8_el12", CPENC (3,5,3,9,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu8_el2", CPENC (3,4,3,9,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu9_el1", CPENC (3,0,3,9,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu9_el12", CPENC (3,5,3,9,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("afgdtu9_el2", CPENC (3,4,3,9,1), 0, AARCH64_FEATURE (POE2)) SYSREG ("afsr0_el1", CPENC (3,0,5,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("afsr0_el12", CPENC (3,5,5,1,0), 0, AARCH64_NO_FEATURES) SYSREG ("afsr0_el2", CPENC (3,4,5,1,0), 0, AARCH64_NO_FEATURES) @@ -391,6 +503,14 @@ SYSREG ("disr_el1", CPENC (3,0,12,1,1), 0, AARCH64_FEATURE (RAS)) SYSREG ("dit", CPENC (3,3,4,2,5), 0, AARCH64_FEATURE (V8_3A)) /* DIT */ SYSREG ("dlr_el0", CPENC (3,3,4,5,1), 0, AARCH64_NO_FEATURES) + SYSREG ("dpocr_el0", CPENC (3,3,4,5,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr0_el1", CPENC (3,0,2,0,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr0_el12", CPENC (3,5,2,0,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr0_el2", CPENC (3,4,2,0,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr0_el3", CPENC (3,6,2,0,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr1_el1", CPENC (3,0,2,0,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr1_el12", CPENC (3,5,2,0,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("dpotbr1_el2", CPENC (3,4,2,0,7), 0, AARCH64_FEATURE (POE2)) SYSREG ("dspsr_el0", CPENC (3,3,4,5,0), 0, AARCH64_NO_FEATURES) SYSREG ("elr_el1", CPENC (3,0,4,0,1), 0, AARCH64_NO_FEATURES) SYSREG ("elr_el12", CPENC (3,5,4,0,1), 0, AARCH64_NO_FEATURES) @@ -418,6 +538,118 @@ SYSREG ("far_el12", CPENC (3,5,6,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("far_el2", CPENC (3,4,6,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("far_el3", CPENC (3,6,6,0,0), 0, AARCH64_NO_FEATURES) + SYSREG ("fgdtp0_el1", CPENC (3,0,3,2,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp0_el12", CPENC (3,5,3,2,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp0_el2", CPENC (3,4,3,2,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp0_el3", CPENC (3,6,3,2,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp10_el1", CPENC (3,0,3,3,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp10_el12", CPENC (3,5,3,3,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp10_el2", CPENC (3,4,3,3,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp10_el3", CPENC (3,6,3,3,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp11_el1", CPENC (3,0,3,3,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp11_el12", CPENC (3,5,3,3,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp11_el2", CPENC (3,4,3,3,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp11_el3", CPENC (3,6,3,3,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp12_el1", CPENC (3,0,3,3,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp12_el12", CPENC (3,5,3,3,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp12_el2", CPENC (3,4,3,3,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp12_el3", CPENC (3,6,3,3,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp13_el1", CPENC (3,0,3,3,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp13_el12", CPENC (3,5,3,3,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp13_el2", CPENC (3,4,3,3,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp13_el3", CPENC (3,6,3,3,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp14_el1", CPENC (3,0,3,3,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp14_el12", CPENC (3,5,3,3,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp14_el2", CPENC (3,4,3,3,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp14_el3", CPENC (3,6,3,3,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp15_el1", CPENC (3,0,3,3,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp15_el12", CPENC (3,5,3,3,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp15_el2", CPENC (3,4,3,3,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp15_el3", CPENC (3,6,3,3,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp1_el1", CPENC (3,0,3,2,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp1_el12", CPENC (3,5,3,2,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp1_el2", CPENC (3,4,3,2,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp1_el3", CPENC (3,6,3,2,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp2_el1", CPENC (3,0,3,2,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp2_el12", CPENC (3,5,3,2,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp2_el2", CPENC (3,4,3,2,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp2_el3", CPENC (3,6,3,2,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp3_el1", CPENC (3,0,3,2,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp3_el12", CPENC (3,5,3,2,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp3_el2", CPENC (3,4,3,2,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp3_el3", CPENC (3,6,3,2,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp4_el1", CPENC (3,0,3,2,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp4_el12", CPENC (3,5,3,2,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp4_el2", CPENC (3,4,3,2,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp4_el3", CPENC (3,6,3,2,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp5_el1", CPENC (3,0,3,2,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp5_el12", CPENC (3,5,3,2,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp5_el2", CPENC (3,4,3,2,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp5_el3", CPENC (3,6,3,2,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp6_el1", CPENC (3,0,3,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp6_el12", CPENC (3,5,3,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp6_el2", CPENC (3,4,3,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp6_el3", CPENC (3,6,3,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp7_el1", CPENC (3,0,3,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp7_el12", CPENC (3,5,3,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp7_el2", CPENC (3,4,3,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp7_el3", CPENC (3,6,3,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp8_el1", CPENC (3,0,3,3,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp8_el12", CPENC (3,5,3,3,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp8_el2", CPENC (3,4,3,3,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp8_el3", CPENC (3,6,3,3,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp9_el1", CPENC (3,0,3,3,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp9_el12", CPENC (3,5,3,3,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp9_el2", CPENC (3,4,3,3,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtp9_el3", CPENC (3,6,3,3,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu0_el1", CPENC (3,0,3,4,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu0_el12", CPENC (3,5,3,4,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu0_el2", CPENC (3,4,3,4,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu10_el1", CPENC (3,0,3,5,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu10_el12", CPENC (3,5,3,5,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu10_el2", CPENC (3,4,3,5,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu11_el1", CPENC (3,0,3,5,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu11_el12", CPENC (3,5,3,5,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu11_el2", CPENC (3,4,3,5,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu12_el1", CPENC (3,0,3,5,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu12_el12", CPENC (3,5,3,5,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu12_el2", CPENC (3,4,3,5,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu13_el1", CPENC (3,0,3,5,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu13_el12", CPENC (3,5,3,5,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu13_el2", CPENC (3,4,3,5,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu14_el1", CPENC (3,0,3,5,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu14_el12", CPENC (3,5,3,5,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu14_el2", CPENC (3,4,3,5,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu15_el1", CPENC (3,0,3,5,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu15_el12", CPENC (3,5,3,5,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu15_el2", CPENC (3,4,3,5,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu1_el1", CPENC (3,0,3,4,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu1_el12", CPENC (3,5,3,4,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu1_el2", CPENC (3,4,3,4,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu2_el1", CPENC (3,0,3,4,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu2_el12", CPENC (3,5,3,4,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu2_el2", CPENC (3,4,3,4,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu3_el1", CPENC (3,0,3,4,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu3_el12", CPENC (3,5,3,4,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu3_el2", CPENC (3,4,3,4,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu4_el1", CPENC (3,0,3,4,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu4_el12", CPENC (3,5,3,4,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu4_el2", CPENC (3,4,3,4,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu5_el1", CPENC (3,0,3,4,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu5_el12", CPENC (3,5,3,4,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu5_el2", CPENC (3,4,3,4,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu6_el1", CPENC (3,0,3,4,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu6_el12", CPENC (3,5,3,4,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu6_el2", CPENC (3,4,3,4,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu7_el1", CPENC (3,0,3,4,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu7_el12", CPENC (3,5,3,4,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu7_el2", CPENC (3,4,3,4,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu8_el1", CPENC (3,0,3,5,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu8_el12", CPENC (3,5,3,5,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu8_el2", CPENC (3,4,3,5,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu9_el1", CPENC (3,0,3,5,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu9_el12", CPENC (3,5,3,5,1), 0, AARCH64_FEATURE (POE2)) + SYSREG ("fgdtu9_el2", CPENC (3,4,3,5,1), 0, AARCH64_FEATURE (POE2)) SYSREG ("fgwte3_el3", CPENC (3,6,1,1,5), 0, AARCH64_FEATURE (V9_4A)) /* FGWTE3 */ SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES) @@ -635,7 +867,17 @@ SYSREG ("id_pfr1_el1", CPENC (3,0,0,1,1), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("id_pfr2_el1", CPENC (3,0,0,3,4), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("ifsr32_el2", CPENC (3,4,5,0,1), 0, AARCH64_NO_FEATURES) + SYSREG ("irtbrp_el1", CPENC (3,0,2,0,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbrp_el12", CPENC (3,5,2,0,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbrp_el2", CPENC (3,4,2,0,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbrp_el3", CPENC (3,6,2,0,5), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbru_el1", CPENC (3,0,2,0,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbru_el12", CPENC (3,5,2,0,4), 0, AARCH64_FEATURE (POE2)) + SYSREG ("irtbru_el2", CPENC (3,4,2,0,4), 0, AARCH64_FEATURE (POE2)) SYSREG ("isr_el1", CPENC (3,0,12,1,0), F_REG_READ, AARCH64_NO_FEATURES) + SYSREG ("ldstt_el1", CPENC (3,0,2,1,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("ldstt_el12", CPENC (3,5,2,1,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("ldstt_el2", CPENC (3,4,2,1,7), 0, AARCH64_FEATURE (POE2)) SYSREG ("lorc_el1", CPENC (3,0,10,4,3), 0, AARCH64_FEATURE (LOR)) SYSREG ("lorea_el1", CPENC (3,0,10,4,1), 0, AARCH64_FEATURE (LOR)) SYSREG ("lorid_el1", CPENC (3,0,10,4,7), F_REG_READ, AARCH64_FEATURE (LOR)) @@ -1072,6 +1314,10 @@ SYSREG ("spsr_svc", CPENC (3,0,4,0,0), F_DEPRECATED, AARCH64_NO_FEATURES) SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES) SYSREG ("ssbs", CPENC (3,3,4,2,6), 0, AARCH64_FEATURE (SSBS)) + SYSREG ("stindex_el1", CPENC (3,0,4,0,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("stindex_el12", CPENC (3,5,4,0,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("stindex_el2", CPENC (3,4,4,0,2), 0, AARCH64_FEATURE (POE2)) + SYSREG ("stindex_el3", CPENC (3,6,4,0,2), 0, AARCH64_FEATURE (POE2)) SYSREG ("svcr", CPENC (3,3,4,2,2), 0, AARCH64_FEATURE (SME)) SYSREG ("tco", CPENC (3,3,4,2,7), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES) @@ -1094,7 +1340,17 @@ SYSREG ("tfsr_el2", CPENC (3,4,5,6,0), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tfsr_el3", CPENC (3,6,5,6,0), 0, AARCH64_FEATURE (MEMTAG)) SYSREG ("tfsre0_el1", CPENC (3,0,5,6,1), 0, AARCH64_FEATURE (MEMTAG)) + SYSREG ("tindex_el0", CPENC (3,3,4,0,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tindex_el1", CPENC (3,0,4,0,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tindex_el12", CPENC (3,5,4,0,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tindex_el2", CPENC (3,4,4,0,3), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tindex_el3", CPENC (3,6,4,0,3), 0, AARCH64_FEATURE (POE2)) SYSREG ("tpidr2_el0", CPENC (3,3,13,0,5), 0, AARCH64_FEATURE (SME)) + SYSREG ("tpidr3_el0", CPENC (3,3,13,0,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tpidr3_el1", CPENC (3,0,13,0,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tpidr3_el12", CPENC (3,5,13,0,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tpidr3_el2", CPENC (3,4,13,0,0), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tpidr3_el3", CPENC (3,6,13,0,0), 0, AARCH64_FEATURE (POE2)) SYSREG ("tpidr_el0", CPENC (3,3,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el1", CPENC (3,0,13,0,4), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el2", CPENC (3,4,13,0,2), 0, AARCH64_NO_FEATURES) @@ -1340,6 +1596,13 @@ SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), F_REG_128, AARCH64_NO_FEATURES) SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_REG_128, AARCH64_NO_FEATURES) SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_REG_128, AARCH64_FEATURE (V8A)) + SYSREG ("tttbrp_el1", CPENC (3,0,10,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbrp_el12", CPENC (3,5,10,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbrp_el2", CPENC (3,4,10,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbrp_el3", CPENC (3,6,10,2,7), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbru_el1", CPENC (3,0,10,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbru_el12", CPENC (3,5,10,2,6), 0, AARCH64_FEATURE (POE2)) + SYSREG ("tttbru_el2", CPENC (3,4,10,2,6), 0, AARCH64_FEATURE (POE2)) SYSREG ("uao", CPENC (3,0,4,2,4), 0, AARCH64_FEATURE (V8_1A)) /* UAO */ SYSREG ("vbar_el1", CPENC (3,0,12,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vbar_el12", CPENC (3,5,12,0,0), 0, AARCH64_NO_FEATURES) @@ -1350,6 +1613,7 @@ SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_FEATURE (V9_2A)) /* MEC */ SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_FEATURE (V9_2A)) /* MEC */ SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES) + SYSREG ("vnccr_el2", CPENC (3,4,2,2,1), 0, AARCH64_FEATURE (POE2)) SYSREG ("vncr_el2", CPENC (3,4,2,2,0), 0, AARCH64_FEATURE (V8_3A)) /* NV2 */ SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), 0, AARCH64_FEATURE (V8R)) -- 2.25.1
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