[PATCH] AArch64 v9.7 extensions: FEAT_SVE_B16MM
Sivan Shani
sivan.shani@arm.com
Thu Oct 23 15:15:11 GMT 2025
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Thu Oct 23 15:15:11 GMT 2025
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This patch includes:
- Feature flag for FEAT_SVE_B16MM
- Instruction:
- BFMMLA (non-widening) BFloat16 matrix multiply-accumulate.
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 ++
gas/testsuite/gas/aarch64/sve-b16mm.d | 12 ++++++++++++
gas/testsuite/gas/aarch64/sve-b16mm.s | 4 ++++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-dis-2.c | 18 ++++++++++++++----
opcodes/aarch64-tbl-2.h | 1 +
opcodes/aarch64-tbl.h | 7 +++++++
8 files changed, 43 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve-b16mm.d
create mode 100644 gas/testsuite/gas/aarch64/sve-b16mm.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0ca54c3bd40..eae5b04eb97 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10905,6 +10905,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
{"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
{"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
+ {"sve-b16mm", AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 9683d411ce9..5aaf97353ab 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -343,6 +343,8 @@ automatically cause those extensions to be disabled.
@tab Enable the SVE2 BITPERM Extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-b16mm} @tab
+ @tab Enable the SVE B16MM Extension.
@item @code{sve-bfscale} @tab
@tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
@item @code{sve-f16f32mm} @tab @code{sve}
diff --git a/gas/testsuite/gas/aarch64/sve-b16mm.d b/gas/testsuite/gas/aarch64/sve-b16mm.d
new file mode 100644
index 00000000000..d3d7e19997b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16mm.d
@@ -0,0 +1,12 @@
+#as: -march=armv8-a+sve-b16mm
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+:[ \t]+64e0e000[ \t]+bfmmla[ \t]+z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:[ \t]+64e0e01f[ \t]+bfmmla[ \t]+z31\.h, z0\.h, z0\.h
+ *[0-9a-f]+:[ \t]+64e0e3e0[ \t]+bfmmla[ \t]+z0\.h, z31\.h, z0\.h
+ *[0-9a-f]+:[ \t]+64ffe000[ \t]+bfmmla[ \t]+z0\.h, z0\.h, z31\.h
diff --git a/gas/testsuite/gas/aarch64/sve-b16mm.s b/gas/testsuite/gas/aarch64/sve-b16mm.s
new file mode 100644
index 00000000000..067ab9b6b5a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16mm.s
@@ -0,0 +1,4 @@
+bfmmla z0.h, z0.h, z0.h
+bfmmla z31.h, z0.h, z0.h
+bfmmla z0.h, z31.h, z0.h
+bfmmla z0.h, z0.h, z31.h
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e65b61c3f9c..cc6e6546444 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -263,6 +263,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_TMOP,
/* SME MOP4 instructions. */
AARCH64_FEATURE_SME_MOP4,
+ /* SVE B16MM instructions. */
+ AARCH64_FEATURE_SVE_B16MM,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ecaea2d2fdb..f9ea34c6fc3 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20146,10 +20146,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0111xxxxx111xxxxxxxxxxxxx. */
- return A64_OPID_64e0e400_fmmla_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx111xx0xxxxxxxxxx. */
+ return A64_OPID_64e0e000_bfmmla_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx111xx1xxxxxxxxxx. */
+ return A64_OPID_64e0e400_fmmla_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
else
{
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index 1263f1f9bd8..61cb41d5093 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -3995,5 +3995,6 @@ enum aarch64_opcode_idx
A64_OPID_a1c00018_usmop4s_SME_ZAda_3b_SME_Zn_6_3_SME_Zm_17_3,
A64_OPID_a1c00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zm_17_3,
A64_OPID_a1d00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zmx2_17_3,
+ A64_OPID_64e0e000_bfmmla_SVE_Zd_SVE_Zn_SVE_Zm_16,
A64_OPID_MAX,
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e7b17061d82..26de00acbd0 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3057,6 +3057,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 =
AARCH64_FEATURES (2, SME_MOP4, SME_F8F32);
static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
AARCH64_FEATURES (2, SME_MOP4, SME_I16I64);
+static const aarch64_feature_set aarch64_feature_sve_b16mm =
+ AARCH64_FEATURE (SVE_B16MM);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -3181,6 +3183,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16
#define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32
#define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64
+#define SVE_B16MM &aarch64_feature_sve_b16mm
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
@@ -3510,6 +3513,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE_B16MM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SVE_B16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -7737,6 +7742,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00018, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Zn_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0),
+ /* SVE B16MM instructions. */
+ SVE_B16MM_INSN("bfmmla", 0x64e0e000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0),
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
--
2.43.0
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