UCLA VAST Lab

@UCLA-VAST

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AutoSA: Polyhedral-Based Systolic Array Compiler

C++ 240 36
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

C++ 127 26
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

Python 128 17
Stencil with Optimized Dataflow Architecture Compiler

Python 17 6
An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs

MLIR 60 13

Showing 10 of 82 repositories

UCLA-VAST/multilevel-sabre’s past year of commit activity

Python
4 3 0 0
Updated Mar 11, 2026
tapa Public
TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.

UCLA-VAST/tapa’s past year of commit activity
UCLA-VAST/acap-gemm-sa’s past year of commit activity

C++ 0 MIT 0
0 0
Updated Feb 28, 2026
UCLA-VAST/Phoenix_Artifacts’s past year of commit activity

C++ 0 MIT 0
0 0
Updated Feb 27, 2026
UCLA-VAST/Prometheus’s past year of commit activity

C++
10
Apache-2.0
4 0 0
Updated Nov 12, 2025
UCLA-VAST/openhw-2025-SAT-FPGA’s past year of commit activity

C++
8
Apache-2.0
1 0 0
Updated Nov 7, 2025
UCLA-VAST/Enola’s past year of commit activity

Python
13
BSD-3-Clause
3 0 0
Updated Nov 4, 2025
Stream-HLS Public
An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs

UCLA-VAST/Stream-HLS’s past year of commit activity

MLIR
60
MIT
13 1 0
Updated Aug 1, 2025
iceberg Public
Enhancing HLS Modeling with Synthetic Data

UCLA-VAST/iceberg’s past year of commit activity

0 0
1 0
Updated Jun 3, 2025
UCLA-VAST/ZAC’s past year of commit activity

Python
17
BSD-3-Clause
7 0 0
Updated May 22, 2025

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