Fixed clock alignment in axi_stream_master vc by olafvandenberg · Pull Request #420 · VUnit/vunit
added 2 commits
December 10, 2018 10:26…one in axi_lite_master before, to keep alignment with the clock edge and make it possible to implement a wait_until_idle. After handling a wait_for_time message, there is a realignment with the clock as well. To still be able to run at full speed, the queue is processed until it is empty before waiting for another rising edge. Added an extra test to the testbench to verify clock alignment. Slightly modified other tests according to changed timing behavior. Added 'wait until idle' to pop before push test to verify it's behavior.
Olaf van den Berg added 2 commits
December 10, 2018 12:15…re with mocked checks. Apparently there is a difference between GHDL and modelsim in this aspect. Modelsim simulation passed without waiting on tvalid='1' and just an extra 'wait until rising_edge(aclk)', ghdl needs more.
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