Muhammed Fazil k faazill

• in/faazill

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1. FPGA Reflex: Event-Driven Safety Layer for Robotic Manipulation

   Verilog

2. A deterministic, low-latency FPGA accelerator for robotic neural policy inference. Implements a 3-layer MLP in Verilog RTL using Q8.8 fixed-point arithmetic for real-time control loops.

   Verilog

3. Hardware accelerator for robotic grasp scoring using Verilog and Python.

   Verilog 1