janschiefer - Overview
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verilog_spi verilog_spi Public
A simple Verilog SPI master / slave implementation featuring all 4 modes.
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stm32_ws2812b_hal_controller stm32_ws2812b_hal_controller Public
Controlling WS2812b RGB LEDS with STM32 HAL and timers
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yew_ssr_client_hybrid_rendering_template yew_ssr_client_hybrid_rendering_template Public
Yew hybrid rendering
Rust 2
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General-Slow-DDR3-Interface General-Slow-DDR3-Interface Public
Forked from ZiyangYE/General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
Verilog 2
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BluePillDemo BluePillDemo Public
Forked from miniwinwm/BluePillDemo
A collection of small example projects tailored for the Blue Pill board created in STM32CubeIDE. No further updates.
C 1
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learn-fpga-amaranth learn-fpga-amaranth Public
Forked from bl0x/learn-fpga-amaranth
Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
Python 1




