Yuriy Gritsenko yuravg

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1. SystemVerilog UVM testbench example

   SystemVerilog 37 13

2. Tcl packages for Quartus Prime System Console(FPGA debugging).

   Tcl 3

3. A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

   Perl 4 1

4. Quartus pin and Cadence Allegro net-list merger

   Python 3 1

5. Collection of scripts for EDA tools

   Shell 7 2

6. My configuration files for Cadence/Allegro

   Common Lisp 7 2